Viterbi译码器的编解码器的设计 用Verilog实现

Service Manual LG TV LCD DISPLAY models 2011

verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language

说明：  Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)

说明：  VC707_MIG_DDR3.sim文件夹中是仿真的文件：testbench和DDR3模型参数 VC707_MIG_DDR3.srcs文件夹中是源文件，包含DDR3的控制、收发模块、顶层文件(VC707_ MIG_ In ddr3.sim folder are simulation files: testbench and DDR3 model parameters VC707_ MIG_ Ddr3.srcs folder is the source file, including DDR3 control, transceiver module, top-level file)

一个vhdl实现的hamming码编码器-an hamming coder using vhdl

利用Cadence Allegro PCB SI进行SI仿真分析(Performed using the Cadence Allegro PCB SI SI simulation analysis)

说明：  Xilinx CORDIC 算法 MATLAB Verilog仿真(arctan.m Kn.m sin_cos.m MATLAB Verilog)

Universal Shift Register

基于FPGA的门级逻辑实现快速乘法运算的verilog源程序。-FPGA-based gate-level logic implementation of rapid multiplication of the verilog source.