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基于FPGA的数字频率计设计
使用飓风开发板,完成了100M,频率计设计,并可在数码管显示
- 2022-02-25 11:23:58下载
- 积分:1
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初学VHDL有用的,了解后对复杂设计有很大帮助.
初学VHDL有用的,了解后对复杂设计有很大帮助.-VHDL beginner useful understanding of the complexity of the design has been inspired by them.
- 2022-08-10 16:58:07下载
- 积分:1
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基于quartus 的一些程序 都是verilog
还是比较有用的
基于quartus 的一些程序 都是verilog
还是比较有用的 -Based on some of the procedures Quartus Verilog are still quite useful
- 2023-02-23 04:30:03下载
- 积分:1
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用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core....
用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company"s paid Multiplier ip core.
- 2022-03-30 14:40:42下载
- 积分:1
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quartusandmodelsim
本文档对quartus与modelsim运用操作描述十分详细,对初学者,会有很大帮助!(Quartus and modelsim this document on the use of operations described in great detail, for beginners, there will be a great help!)
- 2010-08-30 23:51:02下载
- 积分:1
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(2,1,9)卷积编解码器,译码部分采用Vitebi译码算法,设计使用Verilog HDL语言,在Modelsim平台下仿真通过
(2,1,9)卷积编解码器,译码部分采用Vitebi译码算法,设计使用Verilog HDL语言,在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through
- 2022-05-25 02:39:25下载
- 积分:1
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This application note explains the process of eveloping and debugging a hardware...
This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.-This application note explains the process of eveloping and debugging a hardware abstraction layer (HAL) software device driver, to aid device driver development for the HAL of the Altera Nios® II system. The various software development stages are illustrated using the Altera_Avalon_UART as an example hardware device, and an example of a HAL software device driver called my_uart.
- 2022-01-23 11:16:04下载
- 积分:1
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dac
FPGA的驱动并行接口的DAC程序,效率较高。(FPGA-driven parallel interface of the DAC process more efficient.)
- 2011-08-04 21:48:11下载
- 积分:1
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it performs the serail dividing operations
it performs the serail dividing operations
- 2022-11-07 21:55:03下载
- 积分:1
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synthesis-bandstop-filters
本例介绍直接合成带阻滤波器的方法,n阶滤波器能实现n个传输零点(A direct synthesis technique of a new class of bandstop
coupled resonator elliptic filters is presented. Two different
coupling schemes, which both include source–load coupling are
used. The first coupling and routing scheme is the standard folded
structure used in implementing bandpass elliptic filters with
transmission zeros using resonators.)
- 2013-03-12 18:19:01下载
- 积分:1