(2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过

yuv444 与yuv422相互转换verilog语言(yuv444 to yuv422)

说明：  简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)

Multiplexer styles in VHDL

–ABCDE五路输入表示五人的选择，同意为1，不同意为0，以开关形式实现 –有半数以上同意绿灯亮，否则红灯亮。即分别对应输出Y、R为1或0 –参考仿真结果图：10ns|20ns|30ns|40ns|50ns

nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)

RobustVerilog生成verilog工具(RobustVerilog version)

-- State machine for reading data from Dallas 1621 -- -- Testsystem for i2c controller--- State machine for reading data from Dall as 1621---- Testsystem for i2c controller

SystemVerilog For Design (Springer-2nd_Ed-2006)

：随机脉宽调制是解决交流调速系统 中声学噪声的直接有效方法。随机零矢 量分 布是一种很好 的随 机方法，但其不对称的开关函数使其不适用于传统的电流采样方法。通过仿真表明 PWM周期中点采样的方 法无法得到准确的平均值，在分析不对称模式引起的纹波电流对电流平均值影响的基础上，提出了一种适合 于 RZV分布 的电流采样方法 。仿真结果证实该方法简单可行 。 -: Random pulse width modulation speed control system to solve the exchange of acoustic noise in a direct and effective way. Random zero vector distribution is a good random method, but the asymmetrical switching function so that it does not apply to the traditional current sampling methods. PWM cycle through the simulation shows that the mid-point sampling methods can not be an accurate, on average, the analysis of asymmetric mode ripple current caused by the impact on the current average value based on the proposed distribution of a suitable RZV current sampling methods. The simulation results confirmed that the method is simple and feasible.

processor design istruction load pipeline ,hazard