用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core....

qpsk的fpga实现，包含调制和解调部分，使用verilog语言(FPGA implementation of QPSK)

实现电梯的相关控制系统，在开发板EGO1上实现，数码管显示相关的楼层和状态(dianti in verilog)

基于FPGA的电机控制 FPGA-basedMotorControl-FPGA-based motor control FPGA-basedMotorControl

说明：  agilex fpga description

说明：  详细介绍了如何使用ModelSim进行仿真.(it will teach you how to use the ModelSim to simulink.)

// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined-//-*- Mode: Verilog-*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISH

vhdl描述的显示代码 maxplus2开发环境-VHDL description of the display code development environment maxplus2

VHDL 的100例程代码，能够使你熟练掌握VHDL语言的编写(100 routines of VHDL code, enabling you to master the preparation of the VHDL language)

基于ＦＰＧＡ平台，实现了直接数字频率合成。-FPGA-based platform, to achieve a direct digital frequency synthesis.

多倍（次）分频器 请注意: 本例的各个源描述的编译顺序应该是: 52_divider.vhd 52_divider_stim.vhd-Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd