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2018全国大学生FPGA大赛封闭测试上机题
说明: 2018全国大学生FPGA创新设计大赛南京总决赛封闭测试题目,以及自己编写的verilog和testbench,欢迎学习借鉴(The closed test topic of the 2018 National Undergraduate FPGA innovation design competition Nanjing finals, as well as Verilog and testbench compiled by ourselves, are welcome to learn)
- 2020-11-23 22:39:33下载
- 积分:1
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Roy dsd
说明: basic verilog code on siso, piso, sipo
- 2020-06-25 18:40:01下载
- 积分:1
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mp3codec
it is used to compile codec
- 2009-03-04 17:00:53下载
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//led.v
/*
//led.v
/*-------------------------------------
LED显示模块:led(CLK,AF,ADDR,DATA)
功能: 显示
注意事项: 8位LED
参数: CLK:扫妙时钟输入,推荐1kHz
AF:数码管输出,a~h
ADDR:数码管选择位数出,0~2
DATA:显示数据输入0~9999 9999
编写人: 黄道斌
编写日期: 2006/07/13
-------------------------------------*/-//led.v /*------------------------------------- LED Display Module : led (CLK, AF, ADDR. DATA) function : to show : 8 LED parameters : CLK : So Wonderful clock input, Suggest 1kHz AF : digital tube output, a ~ h ADDR : digital control options from the median, 0 ~ 2 DATA : data show that the importation of 0 ~ 9999 9999 prepared : Huang Daobin preparation date : 2006/07/13-------------------------------------*/
- 2022-06-03 00:26:09下载
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This document is formatted UltraEdit document describes some of the original Ult...
这个文件中是UltraEdit的一些格式化文件说明
由于原来的 UltraEdit 不支持 HDL 语言的格式化显示,把文件解压得到的 wordfile.txt替换其安装目录下的 wordfile.txt 文件即可-This document is formatted UltraEdit document describes some of the original UltraEdit as a result of HDL does not support formatting language shows that the document received decompression wordfile.txt replace its installation directory under the document can wordfile.txt
- 2022-09-16 02:20:04下载
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本文件是周立功试验开发板的配套资料,容易学会
本文件是周立功试验开发板的配套资料,容易学会-This document is ZLG test development board supporting information, easy to learn
- 2023-03-21 03:05:05下载
- 积分:1
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使用vhdl实现的1024点的FFT算法
使用vhdl实现的1024点的FFT算法-Using vhdl implementation of the 1024-point FFT algorithm
- 2022-01-30 20:38:46下载
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sparc org, vhdl rtl code
sparc org, vhdl rtl code
- 2022-04-19 15:34:55下载
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发送卡
led 发送卡代码(led send card verilog)
- 2021-04-06 11:19:02下载
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VHDL language used to achieve 8
用VHDL语言实现8-3线编码器,16-4线编码器-VHDL language used to achieve 8-3 line encoder ,16-4-wire encoder
- 2023-08-20 10:35:02下载
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