picoblaze实现串口通信...难道一定要20个字吗?

verilog ADPLL file with testbench.v

Altera的CycloneIII Start Board,使用的PFGA是3C25，包括原理图和PCB，用Cadence Allegro打开-Altera

sequenceur,该模块的主要功能是，控制器，在基本的risc架构中，实现各个模块的控制-sequenceur，control

用VHDL语言实现的ARM处理器的标准内核的源代码程序，可在重用-use of the VHDL standard ARM processor core source code procedures, the reuse

spi通用串行总线，4线控制，可读写操作(SPI universal serial bus, 4-wire control, readable and writable operation)

FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)

利用QuartusⅡ6.0对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。(The Quartus II 6 is used to simulate the VHDL code of the designed taxi billing device, and the control is realized on the FPGA digital experiment system.)

王金明的一些学习VHDL的子-Wang Jinming study of some subset of VHDL

说明：  Matlab源程序，包括插值计算、积分微分等。(Matlab source code, including the interpolation calculations, differential and so on.)

雷达信号产生4PSK简单脉冲信号很好用信号产生(Radar signal pulse signal generating 4PSK simple signal generating good)