Verilog 下 16位除法算法程序，高精度，固定17个时钟周期

ADS7844 AD转换芯片的VHDL控制器-ADS7844 AD converter chip VHDL controller

说明：  i2c module，有i2c主机和从机模块(i2c module verilog VHDL base on i2c protocol)

此两文件是在MAXplusII环境下开发并运行通过的VHDL文件，实现了并串口转换功能。-this document is in two MAXplusII environment through the development and operation of the VHDL documents, and the realization of serial conversion function.

program in hdl that this open mind in digital resources

可以实现对任意波形分任意频，分频加减通过按键实现。-Can be achieved for any arbitrary waveform at frequency, frequency addition and subtraction through the keys to achieve.

这是源代码，该代码为三角波的一代，在 VHDL 写。欢迎下载。谢谢你的支持。

FPGA的卷积编码小程序，VHDL描述，参数为2，1，7.(2,1,7 cov with VHDL.)

offset_cancellation code for matlab to hdl

Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel.

载波同步的verilog代码，是新手学习同步的最佳选择，值得推荐。(Verilog code carrier synchronization, synchronization is the best choice for novices to learn, it is worth recommending.)