适用于FPGA的SOPC方面的程序开发方面，可以用于添加COMPENENT

simple code of some kind of base decoder based on verilog

说明：  文档科斯塔斯环路滤波器。。。。。般若撒根本(wendangsafwrfgvearbeabf)

this is the source code we have been working on for our project using altera de2 board. the code can be run but some of it miss the end game module, while some doesn t have the complete vga code

基于FPGA的快速中值滤波算法,主要使用的语言是verilog 本文没有程序(FPGA-based fast median filtering algorithm, the main language used in this article does not process verilog)

these files are written in verilog but i am uploading in text format

说明：  Verilog HDL语言编写的32位程序计数器（PC）完整工程及相应仿真，QuartusII7.2下编译通过可正常使用。(Complete engineering and simulation of Verilog HDL language of the 32-bit program counter (PC), QuartusII7.2 compiled through normal use.)

H.265的FPGA实现！！使用Verilog语言开发。(H.265 FPGA implementation! Developed using Verilog language.)

可实现两个4bit补码的加法及减法，有溢出提示(adder with overflow hint)

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)

说明：  ask psk 编码调制的vhdl 实现(ask psk coded modulation to achieve the VHDL)