dct1d核心的FPGA实现

turbo码的verilog程序，有意者请下载。(turbo code verilog procedures Interested parties please download.)

Mentor Graphics ModelSim User s Guide Software v6.3g

vhdl code for fir filter

说明：  利用vhdl语言编写的译码器程序，采用两种不同方式(The use of language decoder vhdl program, using two different ways)

AES128 encription vhdl code

FPGA AD采集八路数据，12位分辨率，小梅哥FPGA的开发程序，实测可用(FPGA AD collects eight path data, 12 bit resolution, and the development program of Mayo FPGA.)

高性能FPGA应用领域及其研究，FPGA的开发流程-High-performance FPGA applications and research, FPGA development flow

AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)

说明：  介绍了Displayport规格中lind training的背景研究，设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining the signal integrity becomes increasingly more difficult. For many of todays commonly used video interfaces, there are devices that can be used to assist in this matter. However, the use of such a device is only partially documented in the DisplayPort specification for the receiving image device, which means that the receiving side of the video link is free to choose its own implementation. This report presents, together with background research and design decisions, a suggestion for such an implementation. This implementation would need to be compatible towards a wide range of possible video Source devices and DisplayPort cables.)

本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)