通过VHDL语言的例子，对FPGA的VHDL语言的原型（第七章）是

设计与验证Verilog_实例，经典的HDl书籍，强烈推荐-Design and verification Verilog_ examples Hdl classic books, strongly recommend

低通滤波器（由matlab和simulink两种方法实现）源文件及图片示例(Low-pass filter) source file and photo examples (by the two methods matlab and simulink)

一个八位的并行输入，串行输出的编码器；带有开头结尾帧。(It is an encode with eight palallel input and a serial output.)

FPGA经验总结：时序是设计出来的 我们在做详细设计的时候，对于一些信号的时序肯定会做一些调整的，但是这种时序的调整最多只能波及到本一级模块，而不能影响到整个设计。(FPGA Experience: Timing is designed to do the detailed design of our time, for some signal timing will certainly make some adjustments, but adjust this timing can only spread to up to this level of the module, but not affect the whole design.)

JOP内核字节码获取，很难找的东东，呕血之作-JOP core byte code access, it is difficult to find the price. Zhi for hematemesis

说明：  verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)

运用VC编程的带LCD显示的信号发生器可用三个开个调节输出三个波形(Signal generator can be used three to open a regulator output waveform using VC programming with LCD display)

关于usb调试相关测试 代码，用于测试和适配等(usb coding for testing , verigy, for studing usb and fpga)

实现电梯的相关控制系统，在开发板EGO1上实现，数码管显示相关的楼层和状态(dianti in verilog)

数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on