通过VHDL语言的例子，对FPGA的VHDL语言的原型（第七章）是

vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -vhdl waveform occurred procedures. 4 achieve common sinusoidal waveform, 1.30, sawtooth, square-wave (A, B) the frequency and amplitude control output (square A duty cycle is also controllable), can store data of arbitrary waveform characteristics and able to reproduce the waveform, but also through a variety of linear superposition of the waveform output.

利用FPGA实现的脉宽测试技术,基于VHDL,测试误差为时钟周期-Use of FPGA technology to achieve the pulse-width test, based on VHDL, test error of clock cycles

一个高级培训班的内部资料,非常宝贵,读者可以掌握FPGA的基本思路-A high-level training of internal information, are very valuable, readers can grasp the basic ideas FPGA

Package include hardware implementation of Lz77 algorithm

modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program

基于verilog的LU分解,本文件包括详细的程序代码，运行文件，以及详细的文档(LU decompose based on verilog)

40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )

VHDL fft 源程序，直接运行就可以，很好的一个程序-VHDL fft source code can be run directly, a very good program

class diagram diagram for AIRS

(2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through