通过VHDL语言的例子，对FPGA的VHDL语言的原型（第七章）是

伽罗华域的乘法器的设计，使用有限域设计乘法器(Galois field multiplier design, the use of finite field multiplier design)

说明：  ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)

VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序，采用按键控制循环的速度，慢速循环时间间隔为1S，快速循环时间间隔为200ms。(VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fast cycle time interval is 200ms.)

verilog 我自己写得按单脉冲发生器，通过了综合和仿真，和频率可变的正弦波发生器，-verilog I write by a single pulse generator, through the synthesis and simulation, and variable frequency sine wave generator,

用verilog hdl语言编写的fpga与片外sram 的读写控制(With the verilog hdl language fpga sram chip with read and write control)

此程序基于ADC0809,它是CMOS的8位A/D转换器，片内有8路模拟开关，可控制8个模拟量中的一个进入转换器中。-Connection between ADC 0809, it was the eight CMOS A/D converters. Tablets containing eight analog switches, control eight of analog converters enter a Chinese.

用组合逻辑实现循环除法器。稳定、安全、可靠。(Combinational logic loop divider. Stable, secure, and reliable.)

I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能-I2C control of nuclear design, VHDL language, I/O ports I2C Performance

关于语音通信信道调制的程序代码，是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)