hard work for Dictyophora development. . We hope that the right useful.

说明：  xilinx fpga各版本mmcm/pll动态配置RTL代码，包括testbench(xilinx fpga mmcm/pll drp RTL code, including testbench)

基于Basys2开发板实现VGA输出，PS/2键盘接入的贪吃蛇游戏，键盘上下左右控制方向，小键盘+键控制速度，小键盘回车开始游戏，空格暂停游戏。(Basys2 based development board to achieve VGA output, PS/2 keyboard access Snake game, up and down the keyboard to control the direction, speed control keypad+ key keypad Enter to start the game, pause the game space.)

该工程用verilog编写，已通过串口调试助手调试通过，接收模块采采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。 (The project is written in verilog debugging through serial debugging assistant, adopted 8 times the baud rate sampling data receiver module, better filtering done on the PC spontaneous self-closing function.)

全面了解Linux系统，构建服务器，用Vim写写程序(Fully understand the Linux system, build the server, write programs with Vim.)

状态机的典型饮用，可供学习模仿之用，四个状态，简单易学(State machine of the typical drinking, can be used to learn to imitate, four state, easy to learn)

VHDL 编写的RAM例子-RAM prepared VHDL example

本设计是一个伪随机数发生器。此设计；

UDP / IP上的Spartan3E以太网通信通过斯巴达3E发送UDP数据包到/从我的电脑。

实现米粒状态机 用verilog语言实现状态机的过程(Implement a state machine with a grain of rice verilog state machine language course)

给出了脉冲多普勒雷达相参积累的vhdl程序，可作为参考。主要的是设计思想，看之前得掌握相参积累的原理