hard work for Dictyophora development. . We hope that the right useful.

基于 quartus 2 的 lte 信道估计verilog hdl代码 只有功能仿真 时序仿真自己加sdc文件并且调整testbench的clk才能做出来(Estimated Verilog HDL code based Quartus lte channel only functional simulation timing simulation plus sdc file and adjust the testbench clk to do it)

VERILOG语言速查手册,与VHDL齐名的另外一硬件描述语言(verilog language manuals, and the other enjoying VHDL hardware description language 1)

对赛灵思7系列的三种型号的FPGA进行了综述(xilinx 7 productin overview)

基于VHDL语言的基带线路码产生电路设计（毕业论文），内涵完整的源代码(Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code)

DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M

使用VHDL键盘扫描程序，可以稍微修改一下使用

DSP 程序的测试 很有用的 仪器上面用的-DSP testing procedures very useful in the above apparatus

fft快速傅立叶变换源码-the source of fast fft transform

此代码实现4人表决功能，4人中有三人同意即为通过。(Four voting)

Actel FPGA A3P600最小系统原理图，包含JTAG 、电源和封装 (Actel FPGA A3P600 minimum system schematics, including JTAG, power and packaging)