Turbo码编码译码器的研究及其FPGA实现.

altera公司cycloneII全系列说明书，实用-altera" s cycloneII a full range of manual, practical

FPGA与DAC芯片的SPI接口驱动，实现串行数据的传输。(Realizing the communication between FPGA and DA chip)

ddr3使用教学(DDR3 using teaching)

AD768产生锯齿波的源码，DA转化的最基本操作。(AD768 sawtooth source code, the basic operation of DA conversion.)

verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)

应用背景通用模块，以产生可重构的源时钟频率的传输速率。该模块可用于UART，自定义串口协议等。提供一个时钟发生器模块产生可选 ；-波特利率和；——时钟源（可选择分因素） ；还产生接收 ；——时钟的16倍，8倍，倍，倍的传输波特率 ；关键技术UART，VHDL，FPGA，CPLD programmanle逻辑器件。设备无关的代码

基二8点fftverilog实现。经过modelsim仿真通过(Base 2 fftverilog implementation at 8 o clock. Go through the modelsim simulation)

TI DSP XDS100V3仿真器原理图Rev2.0(TI DSP XDS100V3 schematic Rev2.0)

11阶fir数字滤波器的verilog程序设计，线性相位，系数量化处理(11 order of fir digital filter verilog programming, linear phase, the coefficient quantization)

Nonlinear discrete system identification, It uses a pulse of consumer law, Partial least squares method.