本代码是实现了lwip协议栈,可以移植到其他类型的嵌如式操作系统上

基于Verilog的FPGA时钟分频程序(FPGA clock frequency division program based on Verilog)

quartus 17.1 安装包，我现在用的就是(Quartus 17.1 installation kit, what I am using now is)

FPGA驱动VGA接口显示字符 -FPGA-driven interface VGA display characters

用VHDL语言编写的LDPC码硬件实现语言，相对于verilog的，比较简单-Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple

自己写的位同步实验程序参考，该算法需要发送和接收方的频率比较稳定时，可以很快地达到位同步，且十分稳定。位同步是通信技术的基础之一，希望对大家学习有所帮助。(The program is a reference used for bitsynchro writed by myself.When the both send s and receive s frequency are stable,the program can reach bitsynchro fastly.)

基于FPGA芯片，在Nios II IDE软件的开发环境下写的NIos II 软核uart源代码！-Based on FPGA chip, the Nios II IDE software development environment written in NIos II soft-core uart source code!

说明：  ilx554b型号CCD积分时间程序的设计，包括两座控制信号(program for ilx554b,the driver include two parts single)

这些代码为 对于基本的FPGA使用模块beep进行了例化 在工程 系统级建模时只需要直接调用就好了(The code for the basic FPGA using the module beep instantiated only need to be called directly in the engineering system-level modeling like)

QAM调制模块，可用于Quartus仿真与fpga硬件实现。(QAM Modulation Mode, can be used for Quartus simulation and FPGA.)

nios processor example 1