HDLC控制器

几个fpga竞赛的设计例-Several Example FPGA design contest

实现beep发出1234567的音乐声音-beep 123456

说明：  使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)

交通灯的ＶＥＲＩＬＯＧ实现，含详细中文注释．-Verilog realize traffic lights, with detailed notes in Chinese.

LDPC Encoding Ebook Tetourial code

Wiggler Clone .JTAG Schematic and PCB in Altium Designer Format

FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)

用FPGA分频，做一个有时分秒的时钟，并用数码管显示(FPGA divide a sometimes every minute clock, and digital display)

用IF语句实现秒表功能的代码，显示范围在000至99.9.(Stopwatch function code with the IF statement, displayed in the range of 000 to 99.9.)

用VHDL硬件语言实现的iic顶层控制程序-Using VHDL hardware language to achieve the top level of the IIC control procedures