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cpld 控制 8
cpld 控制 8-32M sdram 控制器 maxII epm570实现。-CPLD control 8-32M sdram controller maxII epm570 realize.
- 2022-02-20 19:59:10下载
- 积分:1
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sample_SPI
这是一个瑞萨R78/G13的SPI演示程序,详细的放置了说明,很有用的源码(This is one of the SPI Renesas R78/G13 demonstration program, placed a detailed description of very useful source)
- 2013-09-03 02:59:19下载
- 积分:1
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codeloc1k
说明: 实现电子密码锁的各项功能,经过编译和仿真(Electronic code lock of the function, the compiler and simulation)
- 2008-11-09 21:24:14下载
- 积分:1
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AHBtoAPB
说明: amba总线桥:ahb to asb!verilog hdl文档加代码,非常全,soc(amba bus bridge: ahb to asb! verilog hdl code for the document plus a very full, soc)
- 2021-01-05 03:48:55下载
- 积分:1
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利用verilog语言设计公共电话共包括以下几个状态:挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块...
利用verilog语言设计公共电话共包括以下几个状态:挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块-The use of public telephones were verilog language design include the following states: hang up, standby, identification, change passwords, call the five states. Includes a detailed source code as well as the design process, the module
- 2022-02-25 00:52:03下载
- 积分:1
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FPGA_SSI
说明: 文档中的verilog代码实现了FPGA与SSI总线的数据协议链接(Verilog code in the document of the FPGA data bus protocol and SSI links)
- 2021-04-19 17:08:51下载
- 积分:1
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RS码译码器
采用VHDL语言实现基于BM算法的RS译码器,附件为整个工程文件,内附波形仿真图。程序在QUARTUS II 9.0下仿真通过
- 2022-06-03 16:19:45下载
- 积分:1
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UART_CESHI
基于VHDL语言的串口发送和接收程序,自己调试通过,并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)
- 2016-08-05 15:27:54下载
- 积分:1
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FPGA测试程序SignalTap
AD9235FPGA编程 可AD采集信号 信号频谱检测 检测任意波形输入(AD9235FPGA programming allows AD to collect signal and spectrum detection and detect arbitrary waveform input.)
- 2020-11-24 20:39:34下载
- 积分:1
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VGA的实现
本代码是实现VGA的显示的,在quartus开发环境下能完整的实现VGA的彩色显示,彩色条纹,通过不同按键来实现不同的效果,对于初学者有很大的帮助。
- 2022-02-16 10:18:55下载
- 积分:1