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verilog时钟分频器~ 50hmz波特率9600bps,使用~
verilog分频器~时钟为50hmz,波特率采用9600bps~-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~
- 2022-06-03 13:21:28下载
- 积分:1
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数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;...
数字式移相信号发生器可以产生预置频率的正弦信号,也可产生预置相位差的两路同频正弦信号,并能显示预置频率或相位差值;-digital phase shifting generator can produce preset frequency sinusoidal signal, Preferences may also have phase difference with the way the two-frequency sinusoidal signal, and can show that the preset frequency or phase difference value;
- 2023-07-21 04:20:04下载
- 积分:1
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这是我自己写的4人表决器源码,在xilinx Spartan3E 上已经调试成功,拿出来与大家分享!...
这是我自己写的4人表决器源码,在xilinx Spartan3E 上已经调试成功,拿出来与大家分享!-that I wrote four voting machine source code, In xilinx Spartan3E debugging has been successful, with the show to share with you!
- 2022-01-27 20:17:47下载
- 积分:1
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利用VHDL实现CPLD(EPM240T100C5)的串口发送程序
利用VHDL实现CPLD(EPM240T100C5)的串口发送程序-Using VHDL realize CPLD (EPM240T100C5) Serial sending procedures
- 2022-12-18 02:35:03下载
- 积分:1
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Giga8b10bv10
说明: altera发布的开源8b10b源代码,vhdl语言描述(altera released the source code open source 8b10b, vhdl language description)
- 2021-01-22 18:18:41下载
- 积分:1
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VHDL的重要PPT资料,对初学者非常有益处
VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners
- 2022-08-23 09:05:36下载
- 积分:1
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常见的几种电机的特征与控制方法
常见的几种电机的特征与控制方法-Several common characteristics of the motor and control method
- 2023-03-02 10:15:03下载
- 积分:1
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1553B总线接口技术研究及FPGA实现
基于FPGA的1553b接口设计详细设计论文(1553B design based on FPGA)
- 2019-04-18 11:02:52下载
- 积分:1
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zuixiangxide_NIOS_kaifajiaocheng
来自于NIOSII的那些事,该书详细地介绍了NIOSS的使用过程,非常适合初学者。(From the NIOSII those things, the book are detailed in this paper NIOSS use process, very suitable for beginners.
)
- 2011-12-13 11:33:57下载
- 积分:1
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阶梯波程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ladder IS
PORT(clk,reset:IN STD_LOGIC;
- 2023-07-31 13:05:03下载
- 积分:1