Verilog

使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)

验证阻塞赋值与非阻塞的赋值赋值过程的先后顺序(Verification of the order of assignment and non blocking assignment)

FPGA UART 发送端程序 verilog语言编写 9600波特率 实用(UART transmit side program verilog language 9600 baud)

用verilog编写在FLEX10K上实现的简易CPU-used in the preparation of Verilog FLEX10K achieve simple CPU

数字时中（VHDL）-Numbers in (VHDL)! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

说明：  现在最流行的RTL设计方法之一，本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)

verilog 双模块算术平均值计算模块，子模块在时钟上升沿技术，高层模块根据当前计数值计算算数平均(verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count)

说明：  基于Basy3的贪吃蛇小游戏，实现了相关功能。(Snake Eating Game Based on Basy3)

VHDL库，仿真时使用的，包括打印，类型转换等实用的操作(Practical operation VHDL library, using simulation, including print, type conversion, etc.)

ADC0809 VHDL控制程序,基于VHDL语言，实现对ADC0809控制.-ADC0809 VHDL control procedures, based on the VHDL language, to achieve control of ADC0809.