对16×16次VHDL实例，如果需要详细的请让我知道

FPGA Verilog HDL 读写SRAM(SRAM FPGA Verilog HDL to read and write)

在altera公司FPGA上自己构建了一个最简单的niosii sopc系统(Altera FPGA company on its own to build a simple system niosii sopc)

AHB to Wishbone memory interface VHDL source code

用于编码器计数，速度能够达到5ms/1圈，速度很快，而且杂波也很好，能够准确应用。已应用在工程中很多年

1．初始状态为4个方向的红灯全亮，时间1秒。 2．东、西方向绿灯亮，南、北方向红灯亮。东、西方向通车，时间30秒。 3．东、西方向黄灯闪烁，南、北方向红灯亮。时间2秒。 4．东、西方向红灯亮，南、北方向绿灯亮。南、北方向通车，时间15秒。 5．东、西方向红灯亮，南、北方向黄灯闪烁。时间2秒。 6．返回2，继续运行。 -1. Initial state for four whole direction of the red lights lit up, a second time. 2. East and West to the green, in the south, north to the red light. West and the East to open in time for 30 seconds. 3. East and West to the blinking yellow light, in the south, north to the red light. Time 2 seconds. 4. East and West to the red light, in the south, north to the green. South and North to the opening time of 15 seconds. 5. East and West to the red light, in the south, north to the flashing yellow light. Time 2 seconds. 6. Return 2, continued to operate.

自己编的VHDL的波形发生器 做信号的可以-BOXING

初学ＶＨＤＬ有用的，了解后对复杂设计有很大帮助．-VHDL beginner useful understanding of the complexity of the design has been inspired by them.

VGA彩条信号显示控制电路设计,能通过vga显示横条纹竖条纹棋盘条纹(VGA color signal display control circuit design)

根据ASMD图设计验证冒泡排序算法。给出设计程序及时序仿真结果，含纸质报告。(According to the ASMD diagram design, verify the bubble sorting algorithm. Give the design procedure and the simulation result in time, including paper report.)

vga，显示彩条，及其简单易懂，适合初学(vga, display color bars, and its easy-to-understand, suitable for beginners)