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HDB3
用Verilog HDL语言进行HDB3编码,并通过Quartus Ⅱ仿真验证(With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ)
- 2020-11-30 11:19:28下载
- 积分:1
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跑马灯
跑马灯-是移位寄存器 有6个灯,无延时entity-Bomadeng-shift register is a six lights, without delay entity
- 2022-09-29 01:55:03下载
- 积分:1
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串并转换程序,由串行输出转换为4位的并行输出
串并转换程序,由串行输出转换为4位的并行输出-String and the conversion process, from the serial output is converted to 4-bit parallel output
- 2022-04-12 06:17:43下载
- 积分:1
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基于DE2开发板的VGA显示模块,仅供大家参考
基于DE2开发板的VGA显示模块,仅供大家参考-DE2 development board based on the VGA display module, for your reference
- 2022-03-21 02:14:24下载
- 积分:1
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Traffic-lights-at-the-crossroads
一种十字路口交通灯在matlab环境中的实现源码(Traffic lights at the crossroads)
- 2013-05-16 10:18:38下载
- 积分:1
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a
说明: 利用FPGA实现SDH开销中帧头A1A2的检测(FPGA implementation using SDH overhead in the frame header detection of A1A2)
- 2010-05-25 21:17:03下载
- 积分:1
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DDS
FPGA实现DDS波形发生器,多种信号的产生,(FPGA realization of DDS waveform generator to produce a variety of signals,)
- 2014-07-20 14:31:22下载
- 积分:1
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CProgrammingforabsolutebeginners_WeLearnFree
ebook verilog HDL programming book
- 2015-12-04 14:39:40下载
- 积分:1
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a lot of examples and test code, useful for beginners, it is easy to get started
有很多例子及测试代码,对初学者很有帮助,很容易上手-a lot of examples and test code, useful for beginners, it is easy to get started
- 2022-02-02 14:25:45下载
- 积分:1
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Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-06-13 02:00:08下载
- 积分:1