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lisa-vhdl2va
通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)
- 2013-12-12 11:17:18下载
- 积分:1
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SineGen
Basic VHDL code to create a sine wave generator for an FPGA board.
- 2014-01-24 01:04:15下载
- 积分:1
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cy68013 vhdl code and usb high speed
cy68013 vhdl code and usb high speed
- 2022-04-25 05:24:27下载
- 积分:1
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dds
说明: 基于fpga的函数发生器设计通过fpga实现正弦波输出(基于fpga的函数发生器)
- 2009-08-01 08:47:29下载
- 积分:1
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wireless
无线通信FPGA设计Matlab Verilog代码(Wireless FPGA design Matlab Verilog code)
- 2011-11-30 21:48:18下载
- 积分:1
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AXI总线接口控制代码
本代码为简单AXI接口控制模块,具备数据的读写等传输功能,对总线传输学习者来说是很好的学习资料,可在此代码基础上进行更复杂功能接口的模块的开发。
- 2022-08-15 09:53:12下载
- 积分:1
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vga_core
Code VHDL for control VGA
FPGA: Xilinx, Altera
- 2012-09-09 10:54:28下载
- 积分:1
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csbar(3) : X"E0000" to X"E01FF"
-- M68008 Address Decoder
-- Address decoder for the m68008
-- asbar must be 0 to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
-- download from www.pld.com.cn & www.fpga.com.cn
--- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn
- 2022-02-26 21:53:57下载
- 积分:1
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iq_balance
调整iq幅度不平衡的模块,可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)
- 2021-04-23 17:48:47下载
- 积分:1
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Verilog的150个经典设计实例
说明: Verilog经典实例.包括洗衣机红路灯、兹自动方麦基、等式子可用(Classic examples of Verilog. Including red street lights for washing machines, ZAM, equation availability)
- 2021-03-17 16:49:20下载
- 积分:1