VHDL 的想法

VHDL实现的读取和写入SDRAM的程序代码，学习的人可以参考下-VHDL implementation SDRAM read and write program code, can refer to the following study

一个简易的频率计，主要用检测在一定范围内的频率，当然频率过大会有误差(A simple frequency meter, mainly used for testing in a range of frequencies, of course, frequency of errors over the General Assembly)

说明：  环路滤波器是通信信号调制解调中最重要的一个部分，环路滤波器设计的好坏将直接影响到接收机的性能指标，二阶锁频辅助三阶锁相环路滤波器可以稳定跟踪具有加加速度的信号源，是现代通信中非常实用的技术，本文中详细编写了单载波信号产生模块、信道噪声模块、数字正交下变频模块、鉴频鉴相模块、环路滤波器模块，并包含了完整的testbench模块，对于初学者非常有用。(Loop filter is the most important part of communication signal modulation and demodulation. The design of loop filter will directly affect the performance index of receiver. The second-order frequency locking assisted third-order phase-locked loop filter can stably track the signal source with acceleration speed, which is a very practical technology in modern communication. In this paper, the single carrier signal generation module and channel noise are written in detail Sound module, digital orthogonal down conversion module, frequency and phase detection module, loop filter module, and contains a complete testbench module, which is very useful for beginners.)

这是一个用VHDL语言实现的非常实用的表决器-This is a VHDL language with the very practical voting machine

正弦波VHDL语言~~~ ~~~ ~~~`-Sine wave VHDL language ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ `

说明：  使用verilog实现的双电梯控制器，1-9层，仿真通过(a bi-elevator controller written in VerilgHDL, which has floor1-9, simulation passed)

TLC5510的驱动程序，采用Verilog语言编写(TLC5510 driver, the use of Verilog language)

verilog 编写的I2C程序，控制D/A的(I2C program written by Verilog to control D/A)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动跟踪(System Generator based image processing engineering, multimedia processing on FPGA source, video-based motion tracking)

这是一个EOS项目中的GFP成帧结构，能够容错，可以配置字节域(This is an EOS project GFP Framing structure, be able to fault-tolerant, can be configured byte domain)