VHDL 的想法

通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)

Basic VHDL code to create a sine wave generator for an FPGA board.

cy68013 vhdl code and usb high speed

说明：  基于fpga的函数发生器设计通过fpga实现正弦波输出(基于fpga的函数发生器)

无线通信FPGA设计Matlab Verilog代码(Wireless FPGA design Matlab Verilog code)

本代码为简单AXI接口控制模块，具备数据的读写等传输功能，对总线传输学习者来说是很好的学习资料，可在此代码基础上进行更复杂功能接口的模块的开发。

Code VHDL for control VGA FPGA: Xilinx, Altera

-- M68008 Address Decoder -- Address decoder for the m68008 -- asbar must be 0 to enable any output -- csbar(0) : X"00000" to X"01FFF" -- csbar(1) : X"40000" to X"43FFF" -- csbar(2) : X"08000" to X"0AFFF" -- csbar(3) : X"E0000" to X"E01FF" -- download from www.pld.com.cn & www.fpga.com.cn --- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn

调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)

说明：  Verilog经典实例.包括洗衣机红路灯、兹自动方麦基、等式子可用(Classic examples of Verilog. Including red street lights for washing machines, ZAM, equation availability)