一些vhdl的简单例子。直接解压，不用密码。

基于VHDL语言的基带线路码产生电路设计（毕业论文），内涵完整的源代码(Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code)

详细讲述TURBO码的FPGA实现原理，可作参考，不是码源(A detailed account of the FPGA implementation of principle of the TURBO code can be used as reference, not source code)

实现pwm波的输出，按键可调占空比的，可通过连接pwm输出值led灯以检测占空比的变化(To realize the output of the PWM wave, key adjustable duty ratio, but through the connection PWM output value led lamp with testing duty ratio changes )

16位CUPIP核,完全运行的好的东西,可以直接拿来用的!-16 CUPIP nuclear, full of good things to run, can be directly used to use!

二进制除法器，采用移位相减的方法实现，位数可调-The source code of a divider

PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF

IIC控制器 for Sopc Builder-IIC controller for Sopc Builder

CAN VHDL Code. Behavioral implementation of CAN bus interface.

verilog vga 图像处理(verilog vga)

IEEE Standard for Verilog 2005