10 0M以太网MAC

FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)

说明：  此程序为调试通过的程序，带有I2C总线功能的程序.(this procedure through the debugging process, with I2C bus function procedures.)

Browser modularization processing, browser modularization combing, browser modularization expansion

VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.

一种基于CPRI标准的WCDMA NoddeB射频光纤拉远接口FPGA设计.pdf (CPRI compliant the WCDMA NoddeB RF fiber pull far from the interface of the FPGA design. Pdf)

这是一本介绍FPGA设计过程中关键问题的资料书,对参加面试或工程设计有一定帮助-This is an FPGA design process, introduce the key issues of information written on the interview or take part in engineering design has a certain extent, help

wavelet transform of a signal,it is important and useful code to trans form frequency to time domain

应用背景通用模块，以产生可重构的源时钟频率的传输速率。该模块可用于UART，自定义串口协议等。提供一个时钟发生器模块产生可选 ；-波特利率和；——时钟源（可选择分因素） ；还产生接收 ；——时钟的16倍，8倍，倍，倍的传输波特率 ；关键技术UART，VHDL，FPGA，CPLD programmanle逻辑器件。设备无关的代码

lcd verilog hdl 源码 可以直接使用，适用modelsim-lcd verilog HDL source

FPGA to design in ECU, very help for engineer