DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。...

基于FPGA的实现小数倍分频代码，广泛应用于数字通信中。-FPGA-based implementation of a small multiple of sub-frequency code, widely used in digital communications.

用VHDL编写的8259控制,供大家使用.-with VHDL control of the preparation of the 8259, for your use.

这是可编程逻辑器件（CPLD）初学者的入门级文章，仅供参考。-This is the programmable logic device (CPLD), the entry-level beginners articles for reference purposes only.

用FPGA中的三速以太网来实现UDP通信，功能强大(With a triple-speed Ethernet in the FPGA to implement UDP communication, powerful)

用verilog写的CORDIC算法实现，很适合做超越函数的运算。通常用于实现正弦乘法，或者坐标变换。-The cordic arithmetic implemented by verilog is adapted to exceed function.It is usually used to implement sine multiplication or coordinate tuansform.

说明：  FSK VHDL FSK调制与解调VHDL程序及仿真(FSK VHDL )

基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能(DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board digital display seconds (60s), points (60min), hours (24hours) time . And has a function to manually adjust the time)

说明：  ADD MOV MOVi SUB四指令cpu设计，qutartus，(Design of four-instruction CPU)

计时范围为59.99秒；有计时开始和停止计时控制，复位控制可以对所有计时进行异步复位；计时结果由四位七段数码管显示。

logic lock 的vhdl源码，altera平台适用。-logic lock the VHDL source code, altera platform.