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222
说明: VHDL BISS,SSI,ENDAT2.2, ENCODER
- 2020-11-24 17:46:39下载
- 积分:1
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uart-for-fpga
Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA.
Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit!
The UART controller was simulated and tested in hardware.
- 2020-06-24 22:00:02下载
- 积分:1
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BCHencodeanddecode
bch 编码和译码,用硬件语言vhdl实现(bch edcode and decoder)
- 2020-06-28 18:00:01下载
- 积分:1
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一个简单的移位寄存器。VHDL语言的,或许会对你有所帮助!
一个简单的移位寄存器。VHDL语言的,或许会对你有所帮助!-A simple shift register. VHDL language, and perhaps will help you!
- 2023-07-05 13:15:03下载
- 积分:1
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基于FPGA的JPEG图像压缩芯片设计
基于FPGA的JPEG图像压缩芯片设计 -FPGA-based JPEG image compression chip design
- 2022-01-28 02:00:46下载
- 积分:1
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mux1
mux one hwich is teh best knwo progerma i n the workdl and ist is the
- 2010-01-25 22:13:37下载
- 积分:1
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e1framerdeframer
E1成帧器和解帧器的FPGA实现源码,测试可用(E1 Framer deframer)
- 2012-12-07 12:10:06下载
- 积分:1
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2011-diansai-E
2011年 电赛 E题 简易数字信号传输性能分析仪FPGA信号发生部分 包括m序列,伪随机序列,曼彻斯特编码 程序 和单片机部分程序(2011 CEC E title simple digital signal transmission performance analyzer FPGA signal part of the program and single-chip part of the program)
- 2012-02-23 10:11:07下载
- 积分:1
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verilog based Real Time clock with manual input implement on fpga
它是一个基于verilog的数字时钟,显示时-分-秒,它可以手动输入,并为时、分和秒分配3个开关第二,它数字时钟频率是实时设置的。我自己用逻辑开发的。。。
- 2022-01-26 02:23:56下载
- 积分:1
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USB 1.1 PHY的代码,verilog语言
USB 1.1 PHY的代码,verilog语言
USB 1.1 PHY的代码,verilog语言
USB 1.1 PHY的代码,verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
- 2022-01-25 23:39:51下载
- 积分:1