这是兼容的CPU 8051 VHDL语言，它不是一个侵权。上帝保佑！

fft变换三个中的一个（站长：三个代码算一个）-fft transformation of a three (head : It is a code 3)

VHDL实现的8位乘法器，所有仿真全部通过-VHDL to achieve 8-bit multiplier

用verilog语言编译的pci协议实现，而且有具体的电路图(Compiled with the verilog language pci protocol implementation, but also the specific circuit)

基4FFT原理及MATLAB实现，基本原理，编程思想等(base——4 FFT principle and MATLAB implementation, the basic principles of programming ideas, etc.)

本章介绍了两个EDA技术的综合应用设计实例:数字闹钟和直接数字频率合成器DDS。-EDA chapter describes the two technologies integrated application design example: digital alarm clock and direct digital synthesizer DDS.

说明：  简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)

这个是永磁无刷直流电机的本体结构和控制电路的联合仿真，既可以设计电机的结构，又可以搭电机的控制系统。(This is the body structure of the permanent magnet brushless DC motor and control circuit co-simulation, both the structure of the motor can be designed, they can take control of the motor system.)

这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序-VHDL and FPGA prepared by the computer serial communication procedures and an LED procedures

包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。(Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.)

4位MCU AM2901的完整VHDL程序，AM2901为主程序，其他为实体库-4 MCU AM2901 complete VHDL program, AM2901-based procedures, other entities, the Treasury