这是兼容的CPU 8051 VHDL语言，它不是一个侵权。上帝保佑！

以嵌入式CPU和FPGA为基础的嵌入式系统架构-Embedded CPU and FPGA-based embedded system architecture

sequenceur,该模块的主要功能是，控制器，在基本的risc架构中，实现各个模块的控制-sequenceur，control

用Verilog语言实现了UART串行通信协议(Verilog language used to achieve a UART serial communication protocol)

（1）MTI （2）用FFT实现MTD （3）用FIR滤波器实现MTD ((1) MTI (2) using FFT realization MTD (3) with the FIR filter implementation MTD)

verilog中调用门级电路的实验程序，实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode

USB转RS232RSTTLRS485FT232+SP213串口的原理图AD画的(USB to RS232RSTTLRS485FT232+SP213 serial port schematic AD drawing)

一个采用IIC协议，从ROM里面读数据的接口程序，采用verilog语言，状态机实现。(One with IIC protocol, which read data from ROM interface program, using verilog language, the state machine implementation.)

基于VHDL语言的设计8位CISC微处理器实例-VHDL design language based on 8-bit CISC microprocessor examples

基于VHDL语言的并串转换程序，有四位的并行输出转换为串行输出-Based on the VHDL language and string conversion process, there are four parallel output is converted to serial output

这是基于MIMO-OFDM的同步算法研究的源程序。本程序采用的极大似然估计的方法。(This is based on MIMO-OFDM synchronization algorithm source code. The program uses the method of maximum likelihood estimates. )