write VHDL 8051 kernel, available, convenient, can be downloaded interested in t...

六层的电梯控制系统 用VHDL描述同时还附有系统仿真图形

codic algorithm,which is used to calculate triangular functions

FPGA——IP_RAM实验： 创建IPRAM核，单端口，10位地址线（256字节），8位数据线（每字节8byte），读写使能 input [9:0] address; input clock; input [7:0] data; input wren; //置1则写入 output [7:0] q; LNXmode：控制LEDC显示 1：mode1，从k1~k3输入data的低4位，ledb计时，从0~f，计时跳变沿读取k1~k3的值，存入RAM 8个数之后，从RAM输出数据，用leda显示，同样每秒变化一次(The experiment of FPGA-IP_RAM: Create IPRAM core, single port, 10 bit address line (256 bytes), 8 bit data line (8 byte per byte), read and write enablement)

实用Verilog编写的SVPWM程序，产生出SVPWM波形，可用于实现同步电机或者异步电机的空间矢量控制算法。(Practical Verilog of SVPWM written procedures, resulting in the SVPWM waveform can be used to implement the space vector control algorithm of the synchronous motor or induction motor.)

FPGA UART transmit and so on

xilinx xc9572 cpld 实现的伺服电机控制器，电机控制输出，和增量编码器读取。-Xilinx xc9572 cpld achieve servo motor controller, motor control output, Incremental encoder and the reader.

VHDL电梯控制器程序设计与仿真，内含原理图和VHDL源码，有助于学习VHFL(VHDL u7535 u68AF u63A7 u5236 u5668 u7A0B u5E8F u8BBE u8BA1 u4E0E u4EFF u771F)

This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.

CODE_VHDL_COUNTING 0 到 9 (慈 0 đến 9 Đếm hiển đoạn 施耐 1 带领 7)

Verilog OTP ROM source code