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DDR2 控制器
下载自opencore网站!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
- 2022-08-10 04:02:14下载
- 积分:1
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modelsim_example_c
modelsim仿真,大量vhdl程序,验证,很有价值!(The ModelSim Simulation, a large number of VHDL procedures, validation, great value!)
- 2013-05-05 15:11:06下载
- 积分:1
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apbi2c_latest.tar
APB总线协议转I2C总线协议的接口IP,verilog代码实现,包含详细testbench(APB bus interface to I2C bus interface IP,verilog code )
- 2020-09-16 10:27:55下载
- 积分:1
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CY7C63723
CY7C63723 功能及其引脚描述,外围电路和仿真数据(The CY7C637 is an 8-bit RISC OTP microcontroller.)
- 2009-07-13 14:30:05下载
- 积分:1
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用VHDL实现视频控制程序,实现对图像的采集和压缩,
用VHDL实现视频控制程序,实现对图像的采集和压缩,-Using VHDL realize video control procedures, to achieve image acquisition and compression,
- 2022-06-30 23:43:11下载
- 积分:1
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ethernet-verilog
非常详细的千兆以太网MAC verilog代码,可以供硬件设计时有关网络的开发参考(Very detailed Gigabit Ethernet MAC verilog code, can be used for hardware design of the network to develop a reference)
- 2020-09-19 11:27:57下载
- 积分:1
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用VHDL语言仿真交通灯
用VHDL语言仿真交通灯
用VHDL语言仿真交通灯
用VHDL语言仿真交通灯-Simulation using VHDL language VHDL language with traffic lights traffic lights Simulation
- 2022-01-26 03:57:23下载
- 积分:1
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FIR filter basic verilog code for implementation
FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
- 2023-05-26 11:10:02下载
- 积分:1
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SPI的核心源代码,verilog
Verilog for SPI Core source code
- 2022-01-25 20:51:31下载
- 积分:1
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PCIe_Lab(ALTERA-V5PCIe)
这一设计实例深入浅出,介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。
(Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.)
- 2020-12-02 18:39:25下载
- 积分:1