altera公司cpld的原理图库(protel格式)

-- Moore State Machine with explicit state encoding -- dowload from: www.fpga.com.cn & www.pld.com.cn--- Moore State Machine with explicit state encoding-- dowload from : www.fpga.com.cn

利用GPIO口模拟I2C通信，驱动富士通MB85RC系列铁电存储器 ** 支持的型号：MB85RC64/64V,MB85RC128/128V,不支持MB85RC16/16V(The master inputs the device address word (8 bits) following the start condition, and then the slave outputs)

msk比特误码率matlab仿真 匹配滤波器(the msk bit error rate matlab simulation matched filter)

这是一个基于可编程逻辑器件的程序，用来实现自动转换量程频率计控制器，该程序在可以再仿真器上仿真实现-This is a programmable logic device based on the procedures used to automatically convert the frequency range of the controller, the program can be in the simulation simulator

说明：  CPU课程设计要求以FPGA开发平台为例，分析 CPU 设计的流程与仿真。 本次开发使用的硬件描述语言是 Verilog 语言，使用的指令系统是一个以 MIPS 指令集为子集的指令系统，共 22 条指令，所用的设计仿真软件Modelsim。(CPU curriculum design requires FPGA development platform as an example to analyze the process and Simulation of CPU design. The hardware description language used in this development is Verilog language, and the instruction system used is an instruction system with MIPS instruction set as a subset, with 22 instructions in total. The design simulation software Modelsim is used.)

32位bit输入的CRC32校验，verilog的代码，以及modelsim的testbench代码(The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench)

通过凌阳16位单片机实现复读机的应用的程序。(By Sunplus 16-bit MCU repeater application process.)

说明：  fpga实现相关滤波算法中的CSK算法，采用仿真的方式验证结果 fpga是xilinx 仿真工具是vivado2018.2 语言是verilog(The CSK algorithm is implemented in FPGA, and the results are verified by simulation FPGA is Xilinx The simulation tool is vivado 2018.2 Language is Verilog)

该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)