智能抢答器

能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写(can complete read or write sdram， only include Verilog code and no simulation files)

阿尔法贝塔滤波器，是卡曼滤波器的简化，比卡曼滤波器速度快。这是一个实例。(aplha-beta filter is filter that faster than kalman filter)

关于FFT算法的FPGA实现（源码），数字信号处理不可少。-FFT algorithm on the FPGA implementation (source code)

TCM解码，VHDL代码，是我在工作中做的工程代码，时序稳定，里面有syn以及软判决的算法，经典-TCM decoder, VHDL code, yes, I do work in the project code, timing stability, There are syn and soft-decision algorithm, classic!

32 bit RISC Processor with 3 stage pipeline

实现有限域中乘法，输入二个普通二级制数，输出在本原多项式的乘法结果(Achieve limited multiplication field, enter the number of two-tier system of two ordinary output in primitive polynomial multiplication results)

组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)

跑马灯led_horse vhdl cpldfpga-led_horse vhdl cpldfpga

基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)

Spartan 3E上的Rotary encoder控制程序，及验证它的小灯程序(Rotary encoder on the Spartan 3E control procedures, and verification procedures for its small light)