Asynchronous FIFO controller Verilog Design and Implementation

地铁售票系统，基于VHDL，可实现站点设置，站点选择，选择购票数量，找零等一系列功能。-Metro ticketing system, based on VHDL, allows site settings, site selection, choose the number of tickets, Keep the change and a series of functions.

锡林克斯巴达官方文件有详细说明，支持斯巴达、顶点

detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.

说明：  高清电子书4本合集-Verilog HDL数字系统设计教程4本合集(Digital circuit design Verilog HDL digital system design)

基于PCF8591数模转换和DDS技术的信号发生器系统设计(Design of Signal Generator System Based on PCF8591 Digital-to-Analog Conversion and DDS Technology)

页面置换算法中的三种算法相关程序代码 FIFO LUR OPT-yemianzhihuansuanfa

TIMING LEARNING -TIMING LEARNING

IIC总线协议，VHDL语言编写，可以直接使用-IIC bus protocol, VHDL language can be used directly

fpga实现ＣＡＮ总线控制器源码,每个项目都有说明文件，介绍使用方法。(fpga CAN Bus Controller source, each with explanatory documents on the use of methods.)

verilog分频器～时钟为50hmz，波特率采用9600bps～-Verilog clock divider ~ 50hmz, using baud rate 9600bps ~