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huawei_verilog
huawei代码编码规范,包含基本的verilog的语法等编码规范,业界经典(Huawei code coding specification, including the basic syntax of the Verilog code, the industry classic)
- 2016-03-15 20:02:57下载
- 积分:1
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Ldpc_DecodeV1
block-LDPC 译码VHDL 源代码(block-LDPC decode VHDL source)
- 2011-09-13 11:28:53下载
- 积分:1
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FIFO
fifo异步串口收发程序 FPGA程序(fifo asynchronous serial transceiver)
- 2014-05-07 21:28:49下载
- 积分:1
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本源码详细介绍了UART的经典实例,敬请下载,谢谢适用
本源码详细介绍了UART的经典实例,敬请下载,谢谢适用-The source described in detail a classic example of UART, please download, Thank you apply
- 2022-03-22 20:09:19下载
- 积分:1
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Rotary Encoder
Reading the Rotary Encoder and indicating the selection through...
Rotary Encoder
Reading the Rotary Encoder and indicating the selection through a LED placed on the front panel.
Events counter for the Rotary Encoder and displaying the events on the front panel
Project: events counter for the rotary encoder and displaying the events on the SSD Pmod (Seven-Segments Display Programable module).
- 2022-05-24 04:15:56下载
- 积分:1
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crc16_8bit.v
FPGA用于实现crc16编码的verlog源程序,用到的请下载。(FPGA is used to achieve the the crc16 the encoding of verlog source code used to download.)
- 2012-11-08 13:45:14下载
- 积分:1
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16 point radix 2
使用 c languageit 的 16 点基 2 fft 代码将 16 点时间域序列转换为频率域
- 2022-10-05 23:25:03下载
- 积分:1
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数码管显示
在FPGA EGO1的口袋平台上实现数码管滚动显示学号的功能(Rolling on the digital tube to display the school number)
- 2021-04-17 10:08:52下载
- 积分:1
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设计了一个异步时钟域间进行通行的模块,并采用Modelsim进行仿真验证,仿真结果满足预期的目的。...
设计了一个异步时钟域间进行通行的模块,并采用Modelsim进行仿真验证,仿真结果满足预期的目的。-Designed an asynchronous clock domains between the passage of the module, and use Modelsim for simulation, the simulation results meet the intended purpose.
- 2022-02-04 07:33:00下载
- 积分:1
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IIC
fpga实现的IIC通信的例程,注释很详细(fpga implementation of serial communication routines, comments in great detail)
- 2021-03-24 16:29:15下载
- 积分:1