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this is code verilog

说明：  PID算法用verilog语言实现，实测可用，由三个模块组成(The PID algorithm is implemented in Verilog language. The actual measurement is available. It consists of three modules.)

本代码是用VERILOG语言描述的AMI码的解码的程序，经过调试是正确的。代码简单易懂。(This code is described in VERILOG language AMI code decoding process, after debugging is correct. Code is easy to understand.)

该程序用来实现电话计时以算取费用，比较简单(telephone cost metering verilog code)

基于Montgoery 算法的RSA,FPGA verilog 实现，有测试文件(Based on Montgoery algorithm for RSA,FPGA verilog implementation，bench file)

本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块-This procedure is a VHDL language electronic code lock function, the entire system is divided into three modules, one for the control module, two for the keyboard display module, three modules for the treatment

采用STC89C52单片机的定时器以实现两路PWM波输出，占空比、频率可调(Microcontroller timer used to achieve STC89C52 two PWM wave output, duty cycle, frequency adjustable)

说明：  ip core of the transceiver gtx

基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。(FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.)

基于Verilog的FPGA设计时序分析约束详细解释与使用方法(FPGA timing constraints)