Xilinx PCIcore have a detailed description of official documents, to support the...

用于实现FPGA硬件开发使用的加法器，需要注意的是用Verilog语言实现的(The adder used to realize FPGA hardware development needs to be realized in Verilog language)

说明：  用于FPGA的I2S接收模块，仅供学习和参考(audio-i2s receive.use fpga.)

verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。(verilog halfband FIR)

Nexys-4-DDR-XADC 开发板demo(Nexys-4-DDR-XADC e.v. Board demo)

cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures

实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)

四间隔频率变化，并循环输出50~51ms之间的频率。(Four-interval frequency changes and the cycle between 50 ~ 51ms output frequency.)

生成一个M伪随机序列码，在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)

jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)

基于CPLD 的光电脉冲码盘 信号四倍频电路设计-CPLD-based electro-optical pulse encoder signals four multiplier circuit design