TIMING LEARNING

LDPC encoding code in 1/2code rate for DVB-T2

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

说明：  基于quartusII的QDPSK调制解调vhdl程序。(Modulation and demodulation based quartusII of QDPSK vhdl program.)

说明：  基于fpga的DDS程序 可输出正弦波 方波 三角波 锯齿波(DDS program based on FPGA can output sinusoidal square wave triangular wave sawtooth wave)

本文是Altera公司编写的dspbuilder的设计方法，但是是英文原版的(This article is prepared by Altera Corporation dspbuilder design method, but it is the original English edition of)

This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)

saber的仿真模型，是一个电源的，经过调试已经成功(The simulation model of the saber, is a power, after commissioning has been successfully)

内有LED译码器，汉明纠错译码器，地址译码器，最高优先译码器，双2－4译码器等VHDL的源代码-decoder, Hamming error correction decoder, address decoder, the highest priority decoder, dual 2-4 decoder such as VHDL source code

用verilog编写的can总线控制器，包括设计参考历程和仿真程序，以及开发文档！(Written by verilog can bus controller, including the design reference course and simulation program, and the development of the document!)