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实现在屏幕上显示绿色和红色相间的水平条纹
实现在屏幕上显示绿色和红色相间的水平条纹。其中,vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)
- 2020-06-24 02:00:02下载
- 积分:1
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VHDL的重要PPT资料,对初学者非常有益处
VHDL的重要PPT资料,对初学者非常有益处-VHDL important PPT information is very useful for beginners
- 2022-05-18 19:20:34下载
- 积分:1
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High-speed-digital-correlator
16位高速数字相关器的VERIOLOG程序,已经编译通过了,可以使用(16-bit high-speed digital correlator VERIOLOG program has been compiled by, you can use)
- 2020-10-09 11:37:34下载
- 积分:1
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vhdl code for decoder and detemines the basic mechanism of gates of decoder
vhdl code for decoder and detemines the basic mechanism of gates of decoder
- 2022-01-25 15:11:52下载
- 积分:1
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EX12
说明: 这是一个用Verilog语言编写的一组程序,主要是熟悉开发板的应用,以及verilog语言(This is a Verilog language with a set of procedures, mainly familiar with the application development board, and the verilog language)
- 2011-03-03 09:38:38下载
- 积分:1
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cn1
在MATLAB的SIMULINK中,用DSPBUILDER实现计数功能,控制LED指示灯.(In MATLAB SIMULINK, DSPBUILDER is used to realize counting function and control LED indicator lamp.)
- 2018-08-16 15:35:47下载
- 积分:1
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ac97 VHDL core
ac97 VHDL core
- 2022-04-09 09:46:28下载
- 积分:1
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VMD642_CPLD
本例程位于 VMD642_CPLD目录中。
使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使
用 Verilog HDL书写,编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)
- 2013-09-13 13:59:52下载
- 积分:1
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biss
绝对位置编码器biss与FPGA之间的通信(Absolute position encoder biss communication with FPGA)
- 2017-08-04 12:10:13下载
- 积分:1
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verilog 写的 “梁祝”乐曲演奏电路
verilog 写的 “梁祝”乐曲演奏电路-verilog wrote " The Butterfly Lovers" music concert circuit
- 2022-02-03 08:31:54下载
- 积分:1