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LatticeECP3_SERDES_PCS_使用指南
LatticeECP3 SERDES/PCS 使用指南(LatticeECP3 SERDES/PCS usage guide)
- 2017-06-13 13:57:27下载
- 积分:1
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VESA Timing
VESA CVT视频参数计算器,输入分辨率和刷新率即可得到需要参数。(VGA Timing Calculator)
- 2020-12-23 14:29:07下载
- 积分:1
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Verilog实现 spi接口的FPGA实现 通过仿真,修改后即可应用
Verilog实现 spi接口的FPGA实现 通过仿真,修改后即可应用-Verilog realize spi interface FPGA to achieve through the simulation, the application can be modified
- 2022-08-14 13:03:16下载
- 积分:1
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CH4CH2CH1VHDL 数字电路参考书所有程序7
CH4CH2CH1VHDL 数字电路参考书所有程序7-CH4CH2CH1VHDL digital circuit reference all proceedings 7
- 2022-07-28 00:29:41下载
- 积分:1
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6_42
An FPGA Implementation of a HoG-based Object Detection Processor
- 2016-04-07 23:42:05下载
- 积分:1
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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分:1
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Verilog Blocking and Non Blocking
Verilog Blocking and Non Blocking
- 2022-01-27 18:34:43下载
- 积分:1
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softdemodulation-of-8psk
讲述软解调很不错的一片文档,主要阐述的是8PSK的软解调FPGA实现,但对8PSK的软解调原理阐述很清楚,没有多余的东西,但需要注意其中各个调制符号点得顺序。(About soft demodulation of a document is very good, mainly on the soft 8PSK demodulation FPGA, but soft 8PSK demodulation principle describes very clearly, no extra stuff, but need to pay attention to the point where each modulation symbol was in order.)
- 2014-06-03 14:12:05下载
- 积分:1
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CAN
说明: ZYNQ中 PS 端 CAN接口的基本使用方法,并通过 CAN接口实现与 PC 端 CA N调试软件之间的数据接收和发送(The basic use method of PS end can interface in zynq, and the data receiving and sending with PC end can debugging software through can interface)
- 2020-04-03 16:41:52下载
- 积分:1
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ahb_verilog_design
代码为ahb interface ,用verilog编写的,包括仿真和综合。(Code for the interface AHB, written in Verilog, including simulation and synthesis.)
- 2020-12-21 14:49:07下载
- 积分:1