VHDL fft 源程序，直接运行就可以，很好的一个程序

DDS中的正余弦生成，初始相位相差90度，可自行改变输出频率(Cosine generation of DDS, the initial phase difference of 90 degrees, the output frequency can be changed on their own)

16QAM调制解调程序画出时域波形、 正交分量、同相分量波形，眼图，散点图等(16QAM modulation and demodulation process to draw time-domain waveform, quadrature components, in-phase component waveforms, eye diagrams, scatter plots, etc.)

FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。(FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.)

说明：  FPGA程序的top.v文件，主要实现DDS信号发生器功能，通过定时器，可简单实现输出幅值无极跳变(FPGA procedures top.v documents, the main function of DDS signal generator, through the timer can be simple to achieve the output amplitude wuji hopping)

VHDL TESTBENCH书写规范，对学习FPGA的同学很有帮助，掌握仿真语言书写规范。(VHDL TESTBENCH description of the norms, the students learn FPGA helpful, master the language of simulation techniques)

FPGA 帧同步源代码 调试无错误 ALTERA 平台(Frame synchronization FPGA)

点亮led流水灯，通过调用锁相环，可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)

关于一个串行数据输入 根据时序将数据分两路输出的程序 -on a serial data input timing will be based on output data using two procedures

关于SPWM调制设计VHDL代码 关于SPWM调制设计VHDL代码(SPWM modulation on the design of VHDL code design on the VHDL code modulation SPWM)

可配置CRC参考设计 xilinx的ip，参考设计文档CRC_xapp562[1].pdf，VHDL语言编写的代码，包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the necessary documents