利用FPGA实现的脉宽测试技术,基于VHDL,测试误差为时钟周期

说明：  Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)

it has 6 packages of 8051 sources,including source code(VHDL and Verilog),dc scripts, pdfs, netlists etc. and a MIPS IP package

本实验主要是在FPGA上实现FIR数字滤波器的功能，不仅有工程文件，还具有论文资料。(This experiment mainly realizes the function of FIR digital filter on FPGA, not only has the engineering document, but also has the thesis information.)

nrf24l01发送代码，verilog实现NRF24L01通信(NRF24L01 send code, Verilog to achieve NRF24L01 communication)

用FPGA单片机软核实现键盘扫描，键盘为4X4矩阵键盘，输入相应键值，用数码管显示-keyboard

一个在CPLD，EPM70128上实现的PWM控制源程序。-A CPLD, EPM70128 realize the PWM control on the source.

存储器DDR3在Xlinix平台上的设计教程和综合应用(Design course and comprehensive application of memory DDR3 on Xlinix platform)

说明：  led学习控制l44444444444444(led verilog led ccccccc)

一些例子程序需要的话可以下来看看新手推荐-Some examples of procedures can be down if necessary to see novice Recommended

此程序完成了FLASH的擦除，读写的功能，并通过USB芯片FT245传送到PC...............................................................................................................................................................................................