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俩个比较好的计数器的vhdl代码:一个是n位通用计数器,一个是的用到的语法比较全面。是比较好的学习资料...
俩个比较好的计数器的vhdl代码:一个是n位通用计数器,一个是的用到的语法比较全面。是比较好的学习资料-Both a relatively good counter VHDL code: one is the generic n-bit counter, one is the syntax used in the more comprehensive. Is a better learning materials
- 2022-02-21 03:30:56下载
- 积分:1
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EDA4--3
实现的电子钟,资料非常全面,是一次课程设计的大作业,完成的质量很高。(Achieve the electronic clock information is very comprehensive, curriculum design job, completed high quality.)
- 2013-01-18 17:41:09下载
- 积分:1
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bubblesort1024ram
说明: 快速冒泡排序基于FPGA实现,有测试文件以及设计图,实现1024*32位数序的多数排序,突破传统是的REG类型少数排序,利用RAM,针对RAM中的无序数的地址调换,达到排序目的,仅供学习交流(Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking tradition is a REG types of minority sorting, the use of RAM, the disorder for the RAM address of the number of exchange, to sort purpose, only to learn the exchange of.)
- 2010-03-24 15:19:50下载
- 积分:1
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add4bit
一位全加器的VHDL源码与TEST BENCH.XILINX下通过(A full adder and the VHDL source code through TEST BENCH.XILINX)
- 2009-07-20 08:18:37下载
- 积分:1
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用verilog写的cpld的各种分频程序,希望大家指正,谢谢!
用verilog写的cpld的各种分频程序,希望大家指正,谢谢!-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!
- 2023-01-20 06:35:04下载
- 积分:1
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高阶矩阵奇异值分解的FPGA实现方法svd_fpga
一种计算高阶矩阵奇异值分解的FPGA实现方法。(A high-end computing matrix singular value decomposition of the FPGA realization method.)
- 2020-07-07 12:28:57下载
- 积分:1
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数字频率计数字频率计
数字频率计
数字频率计-Digital frequency meter digital frequency meter
- 2022-01-24 16:05:05下载
- 积分:1
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chengxu_jieshou
nrf24l01发送代码,verilog实现NRF24L01通信(NRF24L01 send code, Verilog to achieve NRF24L01 communication)
- 2017-08-09 19:04:16下载
- 积分:1
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Compteur_VHDL
VHDL code of a counter
Code VHDL d un compteur
- 2016-07-09 21:00:59下载
- 积分:1
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comp
The red arrow showed the output became 8 when the measured temperature changed to 11°C. As shown by black arrow, the maximum output was 28. The program was run according to the proposed method.
- 2012-06-05 23:16:25下载
- 积分:1