modelsim设计的可调占空比的方波程式

一个用于锁相环开发的资料，请作为参考！-A phase-locked loop for the development of the information, please as a reference!

Program to implement convolution through VHDL-Program to implement convolution through VHDL...

基于FPGA设计的经典打砖块小游戏。游戏简单易玩。(FPGA design based on the classic Arkanoid game. Game easy to play.)

该工程描述的是一位全加器，可以用此作为基础，搭建多位全加器(The project description is a full adder can use this as a basis to build a number of full adder)

说明：  实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)

SPI的VHDL程序，经过quartus验证的，不错！-SPI of the VHDL program, after verification quartus, yes!

串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Verilog)uart 源码 (VHDL)uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) uart source (Verilog) uart source (VHDL) uart16550.tar

verilog源代码，实现两种方法的模3运算。(verilog source code，to implement the calculation of mod-3 by two means.)

用verilog编写的1024点的fft快速傅立叶变换-Verilog prepared using 1024 point fft Fast Fourier Transform

verilog中调用门级电路的实验程序，实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode