Serial to parallel conversion code

verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!

UART RS232 IPCORE for sopc builder -RS232 UART IPCORE for sopc builder

c语言编写51单片机键盘扫描程序，方便移植到其他的硬件上去-51 Singlechip c language keyboard scanning procedures for transplantation to other hardware up

VGA显示接口的verilog控制程序。用于VGA显示器的控制驱动-VGA display interface Verilog control procedures. Control for VGA display driver

fpga永磁同步电机矢量控制系统，包括死区等模块(fpga foc)

１３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用-13 key keyboard VHDL top-level document, I was a novice with the hope that useful for beginners

PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF

OFDM通信系统设计与仿真(shuoshilunwen)(OFDM System Design and Simulation )

axi_lite_user官方样例，精简功能，适用于zynq系列axi总线(Axi_lite_user official sample, streamline function, apply to zynq series Axi bus)

用VHDL编写的8259控制,供大家使用.-with VHDL control of the preparation of the 8259, for your use.