c语言编写51单片机键盘扫描程序，方便移植到其他的硬件上去...

本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)

verilog 典型电路设计包含各种常用电路的源码和详细的解释，适合新手使用(Verilog typical circuit design includes a variety of commonly used circuit source code and detailed explanations, suitable for beginners to use )

用来实现IRIG_B码的解码程序，在XILINX ISE上运行过没有问题，(Used to achieve IRIG_B code decoding process, in XILINX ISE run-off is no problem,)

一个三分频verilog模块，可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)

SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。(SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.)

6713emiftofpgatopci,这个是完整的一套从6713的emif到fpga的双口ram，然后主机通过9054到双口ram，交换数据完成-6713emiftofpgatopci, this is a complete set of the EMIF from 6713 to the FPGA

硬件设计VHDL学习100例(站长推荐)-VHDL hardware design study of 100 cases (chief recommended)

FPGA设计的指导原则，很经典的！希望给大家方便-FPGA design of the guiding principles, it is classic! Want to give everyone easy

VHDL与Verilog的比较-VHDL and Verilog comparison

用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine.