１３键键盘的ＶＨＤＬ顶层文件，我是初学着，希望对初学者有用...

EDA常用计数函数VHDL程序设计，减法计数器：可预置数：-common counting function EDA VHDL programming, subtraction counter : Preset :

24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.

数字秒表的实现，我还写个具体的过程要求等，(there is function of clock,it very useful)

Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!

在altera的FPGA平台上实现rs232串口的自收发通信，速率为115200波特率，PC机使用串口调试助手即可观察结果。包含全部代码与工程，本人亲自测试通过。(Realization of self transmitting and receiving communication serial port of RS232 In altera on the FPGA platform, at a rate of 115200 baud rate, PC using serial debugging assistant can be observed. Contains all the code and engineering, I personally tested by. )

ZBT SRAM控制器参考设计，xilinx提供，（ZBT SRAM是一种高速同步SRAM）-ZBT SRAM controller reference design for Xilinx (ZBT SRAM, a high-speed synchronous SRAM)

一个简单的后台模板，主要为贵金属直播室有喊单等功能类型的。 ps：由于涉及到iframe本地跨域问题，因此查看时请在服务器上进行审阅。(A simple background template, mainly for the precious metal living room, such as the type of function. PS: as a result of the local cross domain problem involved in the iframe, so check it out on the server.)

这篇文章主要是概要的阐述了如何使用-quartusⅡ+Modelsim+synplify pro，来设计FPGA系统。-This is a summary of the main article on how to use the-quartus Ⅱ+ Modelsim+ synplify pro, to design FPGA systems.

电梯控制器程序设计与仿真的vhdl源代码-Elevator controller design and simulation of vhdl source code

基于VHDL可编程BPSk调制教学~~~十分好用`~容易学会-VHDL-based programmable BPSk modulation of teaching is very good ~ ~ ~ `~ easy to learn to