verilog实现ALU的源代码，并提供了详细的测试平台！

FPGA，用VHDL语言产生可调的PWM波(FPGA, VHDL language adjustable PWM wave)

PI控制器的算法及源码，迅速掌握FPGA的VHDL算法实现！(Algorithm and source code of PI controller, quickly grasp the implementation of VHDL algorithm in FPGA!)

Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC

本程序是用verilog 编写的模块，用来在lcd1602上显示用tlc549采样的电压值(This program is written in verilog module, used in lcd1602 display with tlc549 sampled voltage value)

tcp/ip master tcp/ip master tcp/ip master tcp/ip master tcp/ip master tcp/ip master

This an interpolating by 2 half-band filter with 79 taps (40 none-zero coefficients).

VDHL的简单DEMO演示，有利于初学者学习使用(VDHL simple demo DEMO will help beginners learn to use)

This is code of UVM CALLBACK function.

此程序用通过PFGA用VHDL语言实现了傅立叶变换，希望对大家有用

说明：  Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)