verilog实现ALU的源代码，并提供了详细的测试平台！

由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)

NiosII的C代码,包括网卡,lcd,usb,串口,按键.(NiosII C code, including network cards, lcd, usb, serial, key.)

单相的主动式电压质量控制器 对电压跌落进行了补偿(single-phase AVQR for power quility improvement)

完整的OFDM仿真程序，包括QPSK,16QAM调制，基于MATLAB，各个步骤都有详细的说明。(OFDM simulation program, based on the complete MATLAB, every step is described in detail.)

HDLC协议的FPGA实现，运用了VHDL语言，主要就是解封帧HDCL，平切添加了外部接口

AHB master总线verilog实现(Implementation of AHB master bus Verilog)

verilog源代码，实现两种方法的模3运算。(verilog source code，to implement the calculation of mod-3 by two means.)

此文档包含 VHDL 的Vedic 乘数的详细内容。 它内容Vedic 乘数过程的详细的解释。

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ladder IS PORT(clk,reset:IN STD_LOGIC;

Some useful things to know about picoblaze microcontroller.