模块散播聚集 DMA

用verilog hdl语言编写的fpga与片外sram 的读写控制(With the verilog hdl language fpga sram chip with read and write control)

说明：  Digital pre-distortion (DPD) is an advanced digital signal-processing technique that mitigates the effects of power amplifier (PA) nonlinearity in wireless transmitters. DPD plays a key role in providing efficient radio digital front-end (DFE) solutions for 3G/4G basestations and beyond. Modern FPGAs are a promising target platform for the implementation of flexible wireless DFE solutions, including DPD.

Verilog，编写的udp收发程序，开发环境xilinx(Verilog, written UDP transceiver)

设计一个能求出一个32bit字中两个相邻0之间最大间隙的电路。完成HDL设计及testbench描述，给出综合后的时序仿真结果。提交纸质文档。(Design a circuit that can find the maximum gap between two adjacent 0 in a 32bit word. The HDL design and testbench description are completed, and the result of comprehensive simulation is given. Submit paper documents.)

现色彩空间转换R’G’B’ to Y’CbCr的VHDL源代码。-Kabuki现rough cleaning转Connaught distance RGB to Y CbCr cavity VHDL Daitou Tungsten measurements 。

说明：  2020 XILINX Vivado ISE IP License最全最可靠License获取方式。 LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac(LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac)

流水线LMS，和RLS算法的Verilog代码，用于自适应信号处理的FPGA实现。(The Verilog code about fir_pipline_lms and fir_rls. They commonly used in adaptive signal processing in FPGA platform.)

说明：  利用正点院子开拓者fpga实现DDS功能，实现三角波、正弦波、方波的发生。(Implementation of DDS with FPGA)

FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)

在fpga中对于pll无法完成的分频，可采用计数方式，本例用状态机实现对时钟的奇数分频。(Pll in fpga can not be completed in the sub-frequency counting method can be used, in this case with the state machine to achieve an odd number on the clock frequency.)