这是可编程逻辑器件（CPLD）初学者的入门级文章，仅供参考。...

说明：  基于Basy3的贪吃蛇小游戏，实现了相关功能。(Snake Eating Game Based on Basy3)

测试过可用的SD仿真模型，VERILOG语言(SD card simulation modle, test OK)

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)

usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.

verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.

turbo码的编码程序,verilog HDL,在ISE环境中(turbo code encoding process)

使用VHDL语言编程，烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟-The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock

CH2CH1VHDL 数字电路参考书所有程序3-CH2CH1VHDL digital circuit reference all three procedures

altera de2 sd 卡源程序。调试成功的-altera de2 sd card source. Debugging success

用VHDL硬件语言实现的iic顶层控制程序-Using VHDL hardware language to achieve the top level of the IIC control procedures