这是一个很好的USB程序。

VHDL implementation using mouse and monitor

n_bit_paralleLoadShiftRegJK

DDS Verilog 代码。包含英文文档说明-DDS Verilog code. Containing the English documentation

可以实现DDC各个模块的功能，如内插、抽取、FIR滤波等功能(DDC can realize the function of each module, such as interpolation, extraction, FIR filtering)

说明：  Viterbi译码,IS-95中的1/2码率的卷积码(Viterbi decoding, IS-95 of 1/2 the rate Convolutional Codes)

正弦波电流驱动的无刷直流电机性能分析，通过分析方波电流驱动与正弦波电流比较，得出正弦波电流驱动电机性能较好(Sine wave current drive brushless DC motor performance analysis, by analyzing the square-wave current drive with sine wave current comparison, the sine-wave current drive motor performance is better)

nios processor example 1

数字钟的VHDL语言程序，包含了好几个模块，是毕业设计的优秀程序，值得下载！(VHDL language program of digital clock, contains several modules, is an excellent program, graduation design is worth to download!)

说明：  combinatorial modules

LDPC的短码，码长为40速率为0.5的LDPC码的设计，用的是QC矩阵，压缩文件为原码部分，工程太大传不上去。(LDPC short code, a code length of 40 rate of 0.5 LDPC code design, using a QC matrix, the compressed file is part of the original code, do not pass up the works too.)