基于VHDL的LCD显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the LCD display program, including complete source code, locking pin, as well as download files documents can be directly downloaded using

许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等(many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.)

多人抢答器 源代码 实用 课程设计 用用VHDL语言-The source code for more than Responder practical courses designed for use with the VHDL language

常用的锁相环技术，此程序是我在设计高频电路中运用的，具体见程序，经调试无问题-Commonly used phase-locked loop technology, this program is in the design I used in high-frequency circuits, see the specific procedures, no problem by debugging

nios学习资料，fpga调用外部sdram实例，值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)

本代码实现了全加器的功能，可供初学者学习-This code implements a full adder functions, for beginners to learn

说明：  华为FPGA设计全套资料，学习FPGA的朋友可以下载看看。(Huawei FPGA design a full set of materials, friends learning FPGA can download and see.)

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

嵌入式应用开发技术白金手册源代码 嵌入式应用开发技术白金手源代码-this is a vhdf code

这是一个基于Quartus2 开发环境的4输入加法器( 4adder basic on Quartus2)