数字点阵赛车

该文件用在CPLD上的，和C语言很接近，5位的计数器一个。-the documents on the CPLD, and the C language is close to that of the five counters one.

AD7685芯片采集程序，可以自行设置采样率，经检验可用。(The AD7685 chip collection procedures, available.)

利用verilog语言设计公共电话共包括以下几个状态：挂机、待机、身份确认、修改密码、通话等五个状态。内含详细的源码以及设计过程、模块-The use of public telephones were verilog language design include the following states: hang up, standby, identification, change passwords, call the five states. Includes a detailed source code as well as the design process, the module

Multiplexer styles in VHDL

system Verilog combinational logic

F2812串口通信,用于串口通信时使用，可以在线调整(F2812 serial communication, is used for serial communication can be adjusted online)

说明：  基于FPGA的芯片信号发生器，利用Verilog语言实现信号发生器的各个模块单元， 实现的要求：正弦波、三角波、方波等；(Based on FPGA chip signal generator, using Verilog language to realize each module unit of the signal generator, Requirements: sine wave, triangle wave, square wave, etc;)

OQPSK在AWGN和频率选择性衰落信道中的仿真(OQPSK the AWGN and frequency selective fading channel simulation)

这是一个最最常用的用vhdl写的状态机，几乎哪儿都用得到(a very good state machine)

一种合并频率的方法对时频分析及其有用所以才上传(a fast combination)