A complete viterbi coding procedures, the use of VHDL language, as well as test...

A BLIF to VHDL converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included).

《Verilog HDL 程序设计教程》8-"Verilog HDL Design Guide" 8

一个解决除法溢出的例子，可以学习到很多，注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)

JOP内核字节码获取，很难找的东东，呕血之作-JOP core byte code access, it is difficult to find the price. Zhi for hematemesis

说明：  编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现，包含整个QuartusＩＩ的工程文件，解码方式为寄存器交换法(Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange)

VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source

说明：  Verilog 黄金参考指南是 Verilog 硬件描述语言及其语法 语义 合并以及将它应用到硬件设计的一个简明的快速参考指南。(Verilog Golden Reference Guide is a concise and fast reference guide for Verilog Hardware Description Language and its syntax and semantics merging and its application to hardware design.)

FPGA 设计的四种常用思想与技巧-FPGA design ideas and techniques used in four

说明：  用CASE实现4选1数据选择器 很实用 运用VERILOG(Using CASE to achieve 4 election 1 Data Selector practical use Verilog)