A complete viterbi coding procedures, the use of VHDL language, as well as test...

本程序实现不同频率时钟的产生及其相互转化-this program different clock frequencies to the formation and transformation

资源描述该乘法器可用于过滤器，算术运算和；

一个VEILOG HDL程序，可以直接应用，-A VEILOG HDL procedures, can be applied directly,

关于数字电压表的vhdl实现，有仿真程序，可以下载到板子中。(Vhdl digital voltage meter on the implementation of a simulation program can be downloaded to the board.)

CycloneIV控制采样芯片AD9248-20MHz，VHDL语言(CycloneIV control sampling chip AD9248-20MHz, VHDL language)

cic设计 verilog verilog(cic verilog design verilog)

通过VERILOG编写的AD9516时钟芯片SPI配置代码(CONGIGURE THE ad9516)

Meyers wavelet. DWT VHDL.

This code for countor . it is design in verilog HDL.

这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的(This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met)