A complete viterbi coding procedures, the use of VHDL language, as well as test...

学习Xilinx公司开发软件ISE的基础资料，从最基础到复杂逻辑设计。-Learning Xilinx software ISE developed the basis of information from the most basic to complex logic design.

HDB3_verilog编码程序,附有文字解说,格式整齐,便于观看(HDB3_verilog coding procedures)

说明：  ilx554b型号CCD积分时间程序的设计，包括两座控制信号(program for ilx554b,the driver include two parts single)

数控分频器设计:对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。计数器溢出时，输出‘1’电平，同时溢出时的‘1’电平反馈给计数器的输入端作为装载信号；否则输出‘0’电平。 -NC divider design : an adder counter, loading the initial count value, have different frequency output signal of the overflow. Counter overflow, the output"1 "Level, Overflow at the same time the"1 "level feedback to the counter input signal as loading; Otherwise output"0 "level.

Decoder using Miller method for UHF reader

这是用Verilog HDL写的可调占空比分频控制器，可以挂在Avalon总线上使用-This is written in Verilog HDL with adjustable duty cycle frequency controller, can be hung on the Avalon bus use

密码锁，大学数字eda课程顺序锁的源代码，有2位或者4位的顺序锁，可以在fpga或者cpld上实现 (Password lock, digital eda course the order of the source code of the locks, the order of two or four locks, and can be implemented on the fpga or cpld)

MAX2 EPLD 的测试程序, VHDL语言编写.-MAX2 EPLD testing code, VHDL language.

USB设备接口的驱动程序，采用verilogHDL语言编写，并包含相关说明资料(USB device driver interface, using verilogHDL language, and contains descriptive information)

本程序调试了TI的高精度模数转换芯片ADS1115,此模数转换器采用双积分型，16位，为IIC通信方式，调试较复杂，在对直流采集方面有着广泛的应用(This program debugging TI s high-precision analog-digital conversion chip ADS1115)