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Based on VHDL+ FPGA design of the DDS signal gennerator has been through debug mode
一个用VHDL设计的DDS信号发生器,包括两个pics的仿真结果。
- 2022-09-21 09:15:03下载
- 积分:1
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此程序用通过PFGA用VHDL语言实现了傅立叶变换,希望对大家有用...
此程序用通过PFGA用VHDL语言实现了傅立叶变换,希望对大家有用
- 2022-06-25 23:29:26下载
- 积分:1
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2
说明: Objects forming possible solution within original problem context are called phenotypes, their encoding, the individuals within the GA, are called genotypes.
The representation step specifies the mapping the phenotypes onto a set of genotypes.
Candidate solution, phenotype and individual are used to denotes points of the space of possible solutions. This space is called phenotype space.
Chromosome, and individual can be used for points in the genotye space.
Elements of a chromosome are called genes. A value of a gene is called an allele.
Variation Operators
The role of variation operators is to create new individuals old ones. Variation operators form the implementation of the elementary steps with the search space.
- 2014-12-22 22:54:47下载
- 积分:1
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4x4-key
4*4键盘小程序 两种算法内附检查LED(4* 4 keyboard applet containing two algorithms check the LED)
- 2013-07-28 22:19:49下载
- 积分:1
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FPGA的I2S接收模块 audio_in_buff
说明: 用于FPGA的I2S接收模块,仅供学习和参考(audio-i2s receive.use fpga.)
- 2019-04-21 12:11:23下载
- 积分:1
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spi
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )
- 2021-04-29 10:58:43下载
- 积分:1
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Applicable to FPGA
适用于FPGA的SOPC方面的元器件添加,如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT
- 2023-06-11 11:30:03下载
- 积分:1
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Simulation using VHDL language songs Andy Lau
用VHDL语言仿真歌曲刘德华的《月老》
-Simulation using VHDL language songs Andy Lau
- 2023-08-15 11:20:05下载
- 积分:1
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用VERILOG HDL实现的任意 频率分频器源代码,是一个通用的程序...
用VERILOG HDL实现的任意 频率分频器源代码,是一个通用的程序-With VERILOG HDL realize arbitrary frequency divider source code, is a generic procedure
- 2022-03-25 15:26:54下载
- 积分:1
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ATSC发送端部分,ATSC标准特有的TCM编码,共6个文件,包含tb文件,已通过仿真,没有问题,verilog代码...
ATSC发送端部分,ATSC标准特有的TCM编码,共6个文件,包含tb文件,已通过仿真,没有问题,verilog代码-ATSC transmitter, the ATSC standard TCM unique coding, a total of six documents, tb-contained documents, had passed through simulation, no problem, verilog code
- 2022-03-11 13:26:28下载
- 积分:1