此程序用通过PFGA用VHDL语言实现了傅立叶变换，希望对大家有用...

SOC经典教程，包含案例以及完整的代码等等。(SOC classic tutorial, including cases and complete code, and so on.)

说明：  FPGA 点亮数码管的灯，本例程支持6位数码管，因为我的FPGA开发板是这样子的(The lamp of digital tube illuminated by FPGA)

THE SOURCE REALIZE THE TRANSFORMATION FROM YUV TO RGB

this is the source code we have been working on for our project using altera de2 board. the code can be run but some of it miss the end game module, while some doesn t have the complete vga code

软件的使用程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,(very good)

用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)

msk的verilog程序 利用ＦＰＧＡ实现-MSK procedures for the use of Verilog FPGA realize

说明：  通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)

A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.

实现NAND Flash块的控制存取以及同步的FIFO的控制 verilog 代码(NAND Flash control access and control of the synchronous FIFO verilog code)