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wbm
用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.(algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.)
- 2006-07-12 14:49:35下载
- 积分:1
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FPGA DDS
使用DE2实现DDS,步骤简单,配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)
- 2020-06-23 10:00:01下载
- 积分:1
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jjj
实现了四bit计数器的功能,使用的是VHDL语言描述(Four-bit counter, using the VHDL language description)
- 2012-12-20 10:53:46下载
- 积分:1
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XILINX FPGA on internal training materials in Chinese
关于XILINX FPGA
内部
中文培训教材-XILINX FPGA on internal training materials in Chinese
- 2022-05-22 03:01:00下载
- 积分:1
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A_PUF_Design
基于fpga的物理不可克隆函数(PUF)模块的实现(A PUF Design for Secure FPGA-Based Embedded Systems)
- 2014-06-28 15:37:44下载
- 积分:1
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matlab
里面包含了三段代码,主要是用matlab产生高斯随机信号以及高斯白噪声和色噪声,然后计算其数字特征及对这些信号进行频谱分析和功率谱分析,里面还有关于低通滤波器的设计的简单说明(Which contains three sections of code using matlab Gaussian random signals and white Gaussian noise and color noise, and then to calculate the numerical characteristics and spectral analysis and power spectral analysis of these signals, there is also the low-pass filter design BRIEF DESCRIPTION OF)
- 2020-09-22 15:17:51下载
- 积分:1
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LMS自适应均衡器
在通信系统中的信道带来了重要的作用。通道可以涉及许多不同类型的扭曲我们的信息。尤其是无线信道的多径失真严重。而且更严重的是这种失真是随机的。为了解决这个问题,多渠道的影响需要在均衡器接收端。这种均衡器采用不同的学习算法连续识别通道。该项目是VHDL实现LMS学习算法流水线架构。所以这个实施可以工作以更高的数据速率以较少的时钟速度的要求,因此以较少的功耗
- 2022-01-29 00:11:01下载
- 积分:1
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A Dec example written in VHDL.
A Dec example written in VHDL.
- 2022-03-14 22:18:50下载
- 积分:1
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Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL...
买的Altra公司的一款Max II EPM1270T144的电路板,其中的一个用Verilog HDL 编写的驱动数码管的程序,完全可用。-Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL using the digital controls process-driven, fully available.
- 2022-02-16 01:33:54下载
- 积分:1
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dma_hussam
verilog code for dma
- 2021-04-24 19:09:04下载
- 积分:1