Simulation using VHDL language songs Andy Lau

两位独立数码管100进制计数器，每1秒计数一次。从0到99，到99后又回到0.-Two independent 100-band digital tube counters, every time 1 seconds count. From 0 to 99, to 99 and then back to 0.

一个很有用的vhdl实用教程，很适合初学者学习，介绍了vhdl的一些基本概念，还有一些经典的实例。-A useful practical VHDL Tutorial, it is suitable for beginners to learn, introduced some basic concepts of VHDL, there are some classic examples.

用Verlog HDL编写的数字钟程序，包含时，分，秒，进位，解码，扫描显示等功能。-Written by Verlog HDL ，a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.

说明：  Xilinx原语的使用介绍，特别全面，希望对大家有所帮助，(Introduction to the use of Xilinx primitives, particularly comprehensive,I hope it will be helpful to you all.)

说明：  verilog编码器、计数器、加法器的程序(Verilog encoder, counter, adder procedures)

LED灯、跑马灯的显示源程序，包括对代码的说明(Display source code LED lights, marquees, including the code specification)

An FSM using VHDL and Johnson state encoding for states

本代码用verilog语言配合sopc和nios实现了串口调试的目的。软件编程用C语言描述，只是比较简单的例子，适合初学者做了解用，本人亲自在EP2C8Q上实践。(The code to use verilog language sopc and nios achieved with serial debugging purposes. Software programming using C language description, but relatively simple example for beginners to do with understanding, I personally EP2C8Q on practice.)

流水线乘法器与加法器 开发环境：Modelsim（verilog hdl）(Multiplier and adder pipeline development environment: Modelsim (verilog hdl))

sdi音频嵌入及解嵌代码,代码使用Verilog HDL语言(SDI audio embedding and decoding code, the code using Verilog HDL language)