Based on VHDL+ FPGA design of the DDS signal gennerator has been through debug mode

adc0809的fpga时序电路接口程序-Sequential Circuits adc0809 the FPGA interface program

本练习的目的是构建和使用计数器。所设计的电路将在计算机上实现

这是rs（255，223）编码的verilog源程序。里面有：encode、decode、test－bench等文件。(This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.)

使用VHDL语言实现了FPGA与DAC5688进行SPI通信更改寄存器值(The FPGA using VHDL language with the DAC5688 SPI communication to change the register value)

自己完成的项目，成功用vhdl语言实现数字跑表，可存储。

SDRAM的驱动程序，主要是对SDRAM各类状态进行驱动，有刷新模块、读、写模块等。(The driver of SDRAM mainly drives various states of SDRAM, including refresh module, read and write module.)

此两文件是在MAXplusII环境下开发并运行通过的VHDL文件，实现了并串口转换功能。-this document is in two MAXplusII environment through the development and operation of the VHDL documents, and the realization of serial conversion function.

This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery.

基于软输出固定复杂度球形译码的高效迭代检测算法，最新的球形译码论文(Iterative detection algorithm based on a fixed complexity soft-output sphere decoding efficiency, sphere decoding papers)

Example of programming fifo in c