Based on VHDL+ FPGA design of the DDS signal gennerator has been through debug mode

buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键-buffer_display is 4X4KEYPAD output module. It showed six consecutive Press

基于FPGA的键盘程序代码，可用单片机控制-FPGA-based keyboard program code can be used SCM control

基于FPGA的等精度数字频率计，包含FPGA和单片机通信程序，解释非常详细。经过调试成功。(FPGA-based Precision Digital frequency meter, including FPGA and MCU communication program, explained in great detail. After successful commissioning.)

niosII的ip核的实现原理讲解，讲解的非常详细。(niosII ip nuclear realization of the principle of explanation, to explain in great detail.)

调整iq幅度不平衡的模块，可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)

VERILOG实现无分频时钟，包括测试文件，经过验证可用(VERILOG is no difference between the frequency of the clock implementation, including test papers, can be used after authentication)

MaxplusII编写的简易cpu，可实现简单加减法等操作(MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc)

说明：  stm32f103 usart 控制led灯(STM32F103 USART control LED)

组合电路的设计8位加法器设计(ADD8.vhd)-Combinational Circuit Design 8-bit adder design (ADD8.vhd)

全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code