等精度频率计的verilogHDL的实现,我花了好长时间才写的哦

vhdl 语言实例，包括各种逻辑门的构造。-Examples of VHDL language, including a variety of logic gate structure.

说明：  isa MEMORY PLAN eu biu asm

vhdl测试程序，用于初雪者熟悉hdl的具体语法应用。比较简单了。(VHDL test procedure for the First Snow hdl who are familiar with the application of specific syntax. A relatively simple.)

利用matlab提供的firhalfban函数设计阶数为16、通阻带容限为0.0001的半带滤波器。仿真测试滤波前后的信号时域图，回执滤波器的频率响应特性图(Provided firhalfban function using matlab design order of 16, through the 0.0001 stopband wool half-band filter. Simulation test filtered time domain signal before and after, receipt filter frequency response characteristic diagram)

吠陀乘数

一个简单的UCOSII操作系统，在DE2上面调试通过(A simple UCOSII operating systems, debugging through the DE2 above)

wm8731的使用，用于音频信号的采集或者产生(wm8731 use for audio signal acquisition or produce)

I2C端口的FPGA实现，网上较多，但发现不少有问题，这个是在网上代码的基础上修改过，验证可行。-I2C port FPGA, online more, but found that many problems This is a code on the Internet on the basis of the revised test feasible.

FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)

Universal Shift Register