等精度频率计的verilogHDL的实现,我花了好长时间才写的哦

ldpc码的FPGA编译与仿真实现，欢迎分享，分享快乐。(LDPC code compilation and simulation。)

实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency, magnitude controllable output (square wave A, is also a controllable duty cycle), can store arbitrary waveform feature data and can reproduce the waveform, but also completed a variety of linear superposition of the output waveform.

DDR2 SDRAM 控制器的FPGA实现-DDR2 SDRAM controller FPGA to achieve

Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.

FPGA实现四位数与四位数乘法，有仿真波形，合理利用FPGA资源(Four-digit and four-digit multiplication is realized by using FPGA. It has simulation waveform and makes rational use of the resources of the FPGA.)

这个源代码可以把DE2的板子作为一个USB设备使用，以便用PC软件去控制DE2-the source code can Dictyophora the board as a USB device use, to use PC software to control DE2

说明：  SJA1000的ip核和相关测试脚本,OPENCORES 下载(SJA1000 IP downloads from opencores)

一些verilo的经典实例，非常适合初学者(verilo of the classic examples, for beginners)

this is "AND" gate implementation in VHDL

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)