等精度频率计的verilogHDL的实现,我花了好长时间才写的哦

关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL

说明：  uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)

系统介绍EDA技术的发展概述，相关概念，VHDL语言、MAX+PULS、QUARTUS的设计方法。-System overview of the development of EDA technology, related concepts, VHDL language, MAX+ PULS, QUARTUS design method.

Verilog编写的简单异步串口 完全原创，站长请查看内容-Verilog prepared by the simple asynchronous serial completely original, the station can be accessed content

说明：  802.16d 的卷积编码和解码的VHDL实现(802.16d cc encoding and decoding,writing in VHDL)

基于FPGA的红外图像预处理系统的研究与设计，给fpga工程技术人员一个参考-FPGA-based infrared image preprocessing system and design, engineering and technical personnel to fpga a reference

Huffman encoder decoder verilog

vhdl经典源代码――键盘接口设计，入门者必须掌握-vhdl classical source code-- the keyboard interface design, beginners must master

基于NIOS2的VGA接口IP核，具有很好的借鉴性和参考性(NIOS VGA IP)

简单电子玩具的感知模块程序设计,通过外部输入信号改变内部信号.从而改变玩具的状态-simple electronic toys perception module programming, through external input signal a change in the internal signal. In order to change the state of toys