vhdl经典源代码――键盘接口设计，入门者必须掌握

Camera AR0134详细的寄存器配置，以及配置顺序，可以用来初始化摄像头(Camera AR0134 detailed register configuration sequence )

原创，帧同步器的Verilog代码，在FPGA上验证实现过，无误。作为通信系统帧传输的仿真，有限状态机同步态和失步态的切换仿真。(Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine synchronous state and the loss of the switching simulation of gait.)

XVRWARE Library Xilinx Inc. The XVRWARE Synthesis library provides macros and synthesis examples for constructing TMR circuits in VHDL for the Virtex architecture

自己写的布斯4算法的华莱士树无符号数乘法器，3-2压缩，亲测可用(Wallace wrote the number 4 Booth algorithm unsigned multiplier, 3-2 compression, pro-test available)

说明：  FPGA 点亮数码管的灯，本例程支持6位数码管，因为我的FPGA开发板是这样子的(The lamp of digital tube illuminated by FPGA)

设计一个具有同步置1，异步清零的D触发器。 设计一个类似74LS160的计数器(Design an D trigger with synchronous reset 1 and asynchronous reset. Design a counter like 74LS160.)

基于fpga的数字电压表的设计，包括ad转换，bcd码转换，分频，3选1模块，小数点生成模块，显示模块组成。(Based on the FPGA digital voltage meter design, including AD conversion, BCD code conversion, frequency,3 choose1module, a decimal point generating module, display module. )

用Verilog实现的呼吸灯，用Verilog实现的呼吸灯(Verilog huxideng)

64点FFT设计，基于FPGA频域的设计PPT，基4算法(64 point FFT design, based on FPGA frequency domain design, PPT, base 4 algorithm)

适应多个模式的rs编码，Verilog，选择对应的多项式(RS coding adapted to multiple modes.)